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US4700346A
Expired / Lapsed
US
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Self-checking, dual railed, leading edge synchronizer
Assignee: Hewlett Packard Development Co LP
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Filing: 1985-05-10
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Granted: 1987-10-13
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Expires: 2005-05-10
Abstract
Abstract A digital logic circuit and method for synchronizing the leading edges skewed true-complement signal pair. The circuit is comprised of two similar, interconnected circuit halves, each of which includes three D flip-flop stages. The outputs from the second D flip-flop stages from the two circuit halves are applied to the two inputs of two identical logic gates, such that the signal pair is synchronously transmitted to a pair of output gates through a third D flip-flop stage in each circuit half. The second D flip-flop stages also prevent metastable states from reaching the synchronizer output. Metastable states may result if the input setup time is violated for the first D flip-flop stages. The third D flip-flop stage in each circuit half also eliminates any signal irregularities generated in the logic circuitry from appearing on the synchronizer output lines. The circuit is self-checking in that any single fault in the input signals or in the synchronizer circuit itself will result in the synchronizer output pair not having a true complement relationship.
Inventors
- 👤 Srikumar R. Chandran
- 👤 Mark S. Walker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 15:22
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/151; G; G06; G06F; G06F1/00; G06F1/04; G06F1/12; H03K5/13; H03K5/135; H04; H04L; H04L7/00; H04L7/0016; H04L7/0045
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
213 words
An apparatus for synchronizing the leading edges of a pair of digital occurring within a predetermined time period of one another, said apparatus comprising: first means for receiving a first of the pair of digital signals and for storing the logic state of the first of the pair of digital signals, said first means producing a first intermediate signal having a logic state indicative of the leading edge of the first of the pair of digital signals; second means for receiving a second of the pair of digital signals and for storing the logic state of the second of the pair of digital signals, said second means producing a second intermediate signal having a logic state indicative of the leading edge of the second of the pair of digital signals; gate means for receiving the first and second intermediate signals and producing a third intermediate signal indicative of receipt of the leading edges of the pair of digital signals by the first and second means; and output means responsive to the first, second and third intermediate signals to produce therefrom, when the leading edges of the pair of digital signals occur within the predetermined time period, a pair of output signals representative of the pair of digital signals and having synchronized leading edges.
Claim 2
Independent Claim
213 words
An apparatus for synchronizing the leading edges of a pair of digital occurring within a predetermined time period of one another, said apparatus comprising: first means for receiving a first of the pair of digital signals and for storing the logic state of the first of the pair of digital signals, said first means producing a first intermediate signal having a logic state indicative of the leading edge of the first of the pair of digital signals; second means for receiving a second of the pair of digital signals and for storing the logic state of the second of the pair of digital signals, said second means producing a second intermediate signal having a logic state indicative of the leading edge of the second of the pair of digital signals; gate means for receiving the first and second intermediate signals and producing a third intermediate signal indicative of receipt of the leading edges of the pair of digital signals by the first and second means; and output means responsive to the first, second and third intermediate signals to produce therefrom, when the leading edges of the pair of digital signals occur within the predetermined time period, a pair of output signals representative of the pair of digital signals and having synchronized leading edges.
Claim 3
Dependent Claim
21 words
The apparatus claimed in claim 1 wherein each of said first and second means further each comprise two series-connected flip-flop stages.
Claim 4
Dependent Claim
18 words
The apparatus as claimed in claim 1 wherein the pair of digital signals are a true-complement signal pair.
Claim 5
Dependent Claim
26 words
The apparatus as claim 1, including timing means coupled to the first and second means and to the output means for producing a periodic clock signal.
Claim 6
Dependent Claim
36 words
The apparatus of claim 1, the output means including means for placing the output signals in a state indicative of the leading edges of the pair of digital signals not occurring within the predetermined time period.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-10-12 | 1991-04-13 | 1991-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-10-12 | 1995-04-13 | 1995-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-10-12 | 1999-04-13 | 1999-10-13 | $7700.00 | Window Closed / Lapsed |