Digital lattice filter with multiplexed full adder

Claim 1

A digital lattice filter for performing a sequence of arithmetic operations each comprising a multiplication followed by an addition in accordance with a linear predictive coding voice compression technique, comprising: storage means for storing digital arithmetic parameters for use in performing the arithmetic operations; retrieval means for selectively retrieving from said storage means a predetermined one of said stored parameters as a multiplier, a multiplicand or an addend; adder means having first and second inputs and an output for receiving two values and generating the sum thereof on the output; multiplication means for receiving a multiplier and a multiplicand from said retrieval means and generating partial products and for interfacing with said adder means to sum the partial products to perform multiplication and generate a product in accordance with a predetermined multiplication algorithm; first control means for controlling said retrieval means and said multiplication means to retrieve selected ones of said stored multipliers and said stored multiplicands and generate a product; second control means for inputting said product after generation thereof to the first input of said adder means and controlling said retrieval means to retrieve a selected one of said stored addends for input to the second input of said adder means as an addend and controlling said adder to provide the sum thereof, the sum comprising an intermediate arithmetic result; means for controlling the operation of said first and second control means to control the sequence of multiplications and additions to perform a multiplication followed by an addition in a sequence in accordance with the linear predictive coding technique; means for storing each of the intermediate arithmetic results in said storage means in a predetermined order as arithmetic parameters; and means for storing as a final result the final arithmetic operation in the sequence.

Claim 17

An apparatus for performing a sequence of arithmetic operations each comprising a multiplication followed by an addition, comprising: a full adder having first and second inputs and an output for receiving two digital values and generating the sum thereof to provide a summing operation; a system clock for generating system timing reference signals, said reference signals comprising a slow clock signal for determining the duration of time for performing each arithmetic operation and a fast clock signal for determining the duration of each summing operation of said full adder; a rotary data stack for storing predetermined multiplier constants in a predetermined order and incremented by said slow clock to sequentially output said multiplier constants on each cycle of said slow clock; first delay stack means having an input and an output with the input thereof selectively connected to the output of said adder for selectively storing the output therefrom as a multiplicand at the end of each arithmetic operation and outputting the stored multiplicand after a predetermined number of cycles of said slow clock; second delay stack means having an input and an output with the input thereof selectively connected to the output of said adder for selectively storing the output therefrom as an addend at the end of each arithmetic operation and outputting the stored addend after a predetermined number of clock cycles of said slow clock; said first and second delay stack means having a first-in first-out format; temporary data stack means for storing and delaying the results of an arithmetic operation as an addend for one cycle of said slow clock; multiplication means operating in accordance with a modified Booth's algorithm comprising: recode logic means for retrieving the top multiplier value in said rotary data stack in a given one of the arithmetic operations and generating Booth recode logic operators, means for retrieving the top multiplicand value in said first delay stack means and generating partial products in response to the generation of said Booth recode logic operators, and interface means for interfacing with said adder and adding said partial products with said adder to generate the product of said multiplier and multiplicand; adding means for selectively retrieving an addend from the output of either said temporary data stack means or said second delay stack means in accordance with a predetermined pattern and adding said retrieved addend to said product generated by said multiplication means in the given one of the arithmetic operations to provide a result for the given arithmetic operation; and a register for storing the result of the last arithmetic operation in the sequence, said register activated in response to the occurrence of a predetermined number of cycles of said slow clock that defines the length of the sequence.

Claim 18

An apparatus for performing a sequence of arithmetic operations each comprising a multiplication followed by an addition, comprising: a full adder having first and second inputs and an output for receiving two digital values and generating the sum thereof to provide a summing operation; a system clock for generating system timing reference signals, said reference signals comprising a slow clock signal for determining the duration of time for performing each arithmetic operation and a fast clock signal for determining the duration of each summing operation of said full adder; a rotary data stack for storing predetermined multiplier constants in a predetermined order and incremented by said slow clock to sequentially output said multiplier constants on each cycle of said slow clock; first delay stack means having an input and an output with the input thereof selectively connected to the output of said adder for selectively storing the output therefrom as a multiplicand at the end of each arithmetic operation and outputting the stored multiplicand after a predetermined number of cycles of said slow clock; second delay stack means having an input and an output with the input thereof selectively connected to the output of said adder for selectively storing the output therefrom as an addend at the end of each arithmetic operation and outputting the stored addend after a predetermined number of clock cycles of said slow clock; said first and second delay stack means having a first-in first-out format; temporary data stack means for storing and delaying the results of an arithmetic operation as an addend for one cycle of said slow clock; multiplication means operating in accordance with a modified Booth's algorithm comprising: recode logic means for retrieving the top multiplier value in said rotary data stack in a given one of the arithmetic operations and generating Booth recode logic operators, means for retrieving the top multiplicand value in said first delay stack means and generating partial products in response to the generation of said Booth recode logic operators, and interface means for interfacing with said adder and adding said partial products with said adder to generate the product of said multiplier and multiplicand; adding means for selectively retrieving an addend from the output of either said temporary data stack means or said second delay stack means in accordance with a predetermined pattern and adding said retrieved addend to said product generated by said multiplication means in the given one of the arithmetic operations to provide a result for the given arithmetic operation; and a register for storing the result of the last arithmetic operation in the sequence, said register activated in response to the occurrence of a predetermined number of cycles of said slow clock that defines the length of the sequence.

Claim 21

A method for performing a sequence of arithmetic operations each comprising a multiplication followed by an addition in accordance with a linear predictive coding voice compression technique, comprising: storing digital arithmetic parameters as multiplier constants, multiplicands and addends for use in performing the arithmetic operations; selectively retrieving a predetermined one of the stored multipliers and a predetermined one of the multiplicands in accordance with the linear predictive coding technique; generating partial products of the retrieved multiplier and multiplicand in accordance with a predetermined multiplication algorithm; inputting the first and second partial products to the first and second inputs of a full adder to generate the sum therefor constituting the next successive partial product; inputting successive partial products to the inputs of the adder to sequentially sum partial products to provide a generated product in a given one of the arithmetic operations; inputting the generated product into one input of the full adder in the given arithmetic operation; retrieving a predetermined one of the stored addends and inputting it to the second input of the full adder to provide the sum of the retrieved addend with the generated product to provide a result of the given arithmetic operation; performing the addition and multiplication operations in each of the arithmetic operations in the sequence in accordance with the linear predictive coding technique; storing the results of the arithmetic operations as digital arithmetic parameters as either multiplicands or addends in accordance with the linear predictive coding technique; and storing the result of the final arithmetic operation in the sequence in a dedicated register.

Claim 22

A method for performing a sequence of arithmetic operations each comprising a multiplication followed by an addition in accordance with a linear predictive coding voice compression technique, comprising: storing digital arithmetic parameters as multiplier constants, multiplicands and addends for use in performing the arithmetic operations; selectively retrieving a predetermined one of the stored multipliers and a predetermined one of the multiplicands in accordance with the linear predictive coding technique; generating partial products of the retrieved multiplier and multiplicand in accordance with a predetermined multiplication algorithm; inputting the first and second partial products to the first and second inputs of a full adder to generate the sum therefor constituting the next successive partial product; inputting successive partial products to the inputs of the adder to sequentially sum partial products to provide a generated product in a given one of the arithmetic operations; inputting the generated product into one input of the full adder in the given arithmetic operation; retrieving a predetermined one of the stored addends and inputting it to the second input of the full adder to provide the sum of the retrieved addend with the generated product to provide a result of the given arithmetic operation; performing the addition and multiplication operations in each of the arithmetic operations in the sequence in accordance with the linear predictive coding technique; storing the results of the arithmetic operations as digital arithmetic parameters as either multiplicands or addends in accordance with the linear predictive coding technique; and storing the result of the final arithmetic operation in the sequence in a dedicated register.