Patent US4698754A successfully refreshed from Google Patents.
US4698754A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Error detection of scan-out in a diagnostic circuit of a computer
Assignee: Fujitsu Ltd
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Filing: 1983-06-24
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Granted: 1987-10-06
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Expires: 2003-06-24
Abstract
Abstract A data processing system provides a diagnostic circuit having a scan-out function, that includes error checking. A scan-out address check code is generated by a sending unit and another scan-out address check code is generated by a receiving unit. The scan-out address check codes are compared in the sending unit, and an error in the scan-out operation can be detected.
Inventors
- 👤 Minoru Koshino
- 👤 Yasuo Matsumoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 17:56
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/273; G06F11/2736; G06F11/07; G06F11/08; G06F11/10; G06F11/267
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
376 words
A data processing scan-out system using scan-out address information for selecting a circuit to be diagnosed in a scan-out operation, comprising: a first unit, comprising: sending means for sending the scan-out address; first error check information generating means, operatively connected to said sending means, for generating first error check information from the scan-out address information; comparison means, operatively connected to said first error check information generating means, for generating a comparison output indicating error in the scan-out operation; a scan-out address register, operatively connected to said sending means and said first error check generating means, for holding the scan-out address information; first adder means, operatively connected to said scan-out address register, for incrementing the content of said scan-out address register; a count register for counting time; second adder means, operatively connected to said count register, for incrementing the content of said count register; controlling gate means, operatively connected to said first adder and said scan-out address register, for controlling the incrementing of the content of said scan-out address register; decoder means, operatively connected to said count register, for decoding the content of said count register and for generating a set clock signal; and a flip-flop, operatively connected to said comparison means and said decoder, for holding the comparison output of said comparison means until the set clock signal is received from said decoder means; a second unit, operatively connected to said sending means and said comparison means of said first unit, comprising a second error check information generating means for generating second error check information from the scan-out address information and for sending the error check information to said comparison means in said first unit, said comparison means in said first unit comparing the first error check information generated by said first unit with the second error check information sent from said second unit to produce the comparison output; and a third unit, operatively connected to said scan-out address register and said flip-flop in said first unit, for generating initial scan-out address information and for receiving the comparison output, said scan-out address register in said first unit receiving the initial scan-out address information from said third unit and said flip-flop in said first unit sending the comparison output to said third unit during the scan-out operation.
Claim 2
Dependent Claim
376 words
A data processing scan-out system using scan-out address information for selecting a circuit to be diagnosed in a scan-out operation, comprising: a first unit, comprising: sending means for sending the scan-out address; first error check information generating means, operatively connected to said sending means, for generating first error check information from the scan-out address information; comparison means, operatively connected to said first error check information generating means, for generating a comparison output indicating error in the scan-out operation; a scan-out address register, operatively connected to said sending means and said first error check generating means, for holding the scan-out address information; first adder means, operatively connected to said scan-out address register, for incrementing the content of said scan-out address register; a count register for counting time; second adder means, operatively connected to said count register, for incrementing the content of said count register; controlling gate means, operatively connected to said first adder and said scan-out address register, for controlling the incrementing of the content of said scan-out address register; decoder means, operatively connected to said count register, for decoding the content of said count register and for generating a set clock signal; and a flip-flop, operatively connected to said comparison means and said decoder, for holding the comparison output of said comparison means until the set clock signal is received from said decoder means; a second unit, operatively connected to said sending means and said comparison means of said first unit, comprising a second error check information generating means for generating second error check information from the scan-out address information and for sending the error check information to said comparison means in said first unit, said comparison means in said first unit comparing the first error check information generated by said first unit with the second error check information sent from said second unit to produce the comparison output; and a third unit, operatively connected to said scan-out address register and said flip-flop in said first unit, for generating initial scan-out address information and for receiving the comparison output, said scan-out address register in said first unit receiving the initial scan-out address information from said third unit and said flip-flop in said first unit sending the comparison output to said third unit during the scan-out operation.
Claim 3
Dependent Claim
81 words
A data processing scan-out system according to claim 3, wherein said first unit further comprises third error check information generating means, operatively connected to said comparison means and said third unit, for generating third error check information based on the initial scan-out address information sent from said third unit, said comparison means comparing the third error check information from said third error check information generating means with the first error check information generated by said first error check information generating means.
Claim 4
Dependent Claim
208 words
A scan address checking system in a data processing system having a device to be scanned and a scan function, the data processing system providing an input scan address to said scan address checking system, said scan address checking system comprising: a scan address register, operatively connected to receive the input scan address, for storing a registered scan address and providing an operation scan address to the device; and comparison means for comparing the input scan address with the registered scan address and for comparing the register scan address with the operation scan address provided to the device and providing a comparison output indicating whether the register scan address matches the input scan address and the operation scan address, said comparison means comprising: a first parity generator in the device to be scanned, operatively connected to said scan address register, for generating a first parity signal; a second parity generator, operatively connected to said scan address register, for generating a second parity signal; a third parity generator, operatively connected to receive the input scan address, for generating a third parity signal; and a parity comparator, operatively connected to said first, second and third parity generators, for comparing the first and third parity signals with the second parity signal.
Claim 5
Dependent Claim
208 words
A scan address checking system in a data processing system having a device to be scanned and a scan function, the data processing system providing an input scan address to said scan address checking system, said scan address checking system comprising: a scan address register, operatively connected to receive the input scan address, for storing a registered scan address and providing an operation scan address to the device; and comparison means for comparing the input scan address with the registered scan address and for comparing the register scan address with the operation scan address provided to the device and providing a comparison output indicating whether the register scan address matches the input scan address and the operation scan address, said comparison means comprising: a first parity generator in the device to be scanned, operatively connected to said scan address register, for generating a first parity signal; a second parity generator, operatively connected to said scan address register, for generating a second parity signal; a third parity generator, operatively connected to receive the input scan address, for generating a third parity signal; and a parity comparator, operatively connected to said first, second and third parity generators, for comparing the first and third parity signals with the second parity signal.
Claim 6
Dependent Claim
283 words
A scan address checking system in a data processing system having a device to be scanned and a scan function, the data processing system providing an input scan address to said scan address checking system, said scan address checking system comprising: a scan address register, operatively connected to receive the input scan address, for storing a registered scan address and providing an operation scan address to the device; comparison means, operatively connected to said scan address register and to receive the input scan address, for comparing the input scan address with the registered scan address and for comparing the registered scan address with the operation scan address provided to the device and providing a comparison output indicating whether the registered scan address matches the input scan address and the operation scan address, said comparison means comprising: a first parity generator in the device to be scanned, operatively connected to said scan address register, for generating a first parity signal; a second parity generator, operatively connected to said scan address register, for generating a second parity signal; a third parity generator, operatively connected to receive the input scan address, for generating a third parity signal; and a parity comparator, operatively connected to said first, second and third parity generators, for comparing the first and third parity signals with the second parity signal; first gate means, operatively connected to said scan address register and said second parity generator, for selecting portions of the registered scan address for input into said second parity generator; and second gate means, operatively connected to said first and third parity generators and said parity comparator, for selecting between said first and third parity generators for input to said parity comparator.
Claim 7
Dependent Claim
283 words
A scan address checking system in a data processing system having a device to be scanned and a scan function, the data processing system providing an input scan address to said scan address checking system, said scan address checking system comprising: a scan address register, operatively connected to receive the input scan address, for storing a registered scan address and providing an operation scan address to the device; comparison means, operatively connected to said scan address register and to receive the input scan address, for comparing the input scan address with the registered scan address and for comparing the registered scan address with the operation scan address provided to the device and providing a comparison output indicating whether the registered scan address matches the input scan address and the operation scan address, said comparison means comprising: a first parity generator in the device to be scanned, operatively connected to said scan address register, for generating a first parity signal; a second parity generator, operatively connected to said scan address register, for generating a second parity signal; a third parity generator, operatively connected to receive the input scan address, for generating a third parity signal; and a parity comparator, operatively connected to said first, second and third parity generators, for comparing the first and third parity signals with the second parity signal; first gate means, operatively connected to said scan address register and said second parity generator, for selecting portions of the registered scan address for input into said second parity generator; and second gate means, operatively connected to said first and third parity generators and said parity comparator, for selecting between said first and third parity generators for input to said parity comparator.
Claim 8
Dependent Claim
49 words
A scan address checking system in a data processing system as set forth in claim 4, further comprising address update means, operatively connected to said scan address register and said parity comparator, for incrementing the register scan address in said scan address register and for storing the comparison output.
Claim 9
Dependent Claim
109 words
A scan address checking system in a data processing system as set forth in claim 5, wherein said address update means comprises: a first adder operatively connected to said scan address register; a first control gate, operatively connected to said first adder and said scan address register, for updating said scan address register; a count register; a second adder operatively connected to said count register and said first control gate; a second control gate operatively connected to said count register and said second adder; a decoder operatively connected to said count register; and a flip-flop, operatively connected to said parity comparator and said decoder, for holding the comparison output.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-10-05 | 1991-04-06 | 1991-10-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-10-05 | 1995-04-06 | 1995-10-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-10-05 | 1999-04-06 | 1999-10-06 | $7700.00 | Window Closed / Lapsed |