Data processing apparatus having diagnosis function

Claim 2

A data processing apparatus having flip-flop circuits with a self-diagnosis function to permit diagnosis of internal states of operation of the data processing apparatus while the data processing apparatus is in the course of operation comprising: (a) scan-out controlling means for generating a first scan-out address which designates first groups of said flip-flop circuits and receiving scan-out data which are outputs of flip-flop circuits designated by said first scan-out address, each of said first groups consisting of a plurality of second groups of said flip-flop circuits, (b) an address generating circuit receiving said first scan-out address and generating in sequence second scan-out addresses for said second groups of each of said first groups designated by said first scan-out address, (c) bit address generating means for generating a bit address which designates one of said flip-flop circuits, (d) selector means selecting one of said second scan-out address and said bit address, (e) outputting means responsive to said selector means for outputting outputs of said flip-flop circuits, (f) transfer means for transferring said outputs to said scan-out controlling means, and (g) observing means for observing said outputs.

Claim 3

The data processing apparatus according to claim 1, wherein said second group includes a single flip-flop circuit.

Claim 4

The data processing apparatus according to claim 1, wherein said second group includes a plurality of flip-flop circuits, said outputting means provides a plurality of outputs of one of said second groups at the same time, and said observing means has a bit selector which responds to a part of said bit address and selects one of said plurality of outputs.

Claim 5

The apparatus according to claim 1, wherein said selector means is operative to select the bit address from the bit address generating means only during periods when the scan-out controlling means is inoperative.

Claim 6

The apparatus according to claim 4, wherein said selector means repeatedly selects said bit address during periods in which the scan-out controlling means is inoperative so that the observing means can continually monitor the state of the flip-flop designated by said bit address.

Claim 7

A data processing apparatus comprising logic circuits with flip-flop circuits therein and a self-diagnosis circuit for effecting self-diagnosis of internal states of the data processing apparatus while the data processing apparatus is in the course of operation, said self-diagnosis circuit comprising: (a) scan-out control means coupled to a microprocessor and a maintenance panel to generate a first scan-out address which designates one of groups of said flip-flop circuits and adapted to receive scan-out data from the flip-flop circuits of the group designated by said first scan-out address, (b) address generating circuits supplied with said first scan-out address for generating second scan-out addresses bit by bit for the flip-flop circuits of the group designated by said first scan-out address in sequence, (c) a maintenance scan address register settable by said maintenance panel and constantly generating a bit address which designates a specified one of said flip-flop circuits, (d) selection means for selecting one of said second scan-out addresses and said bit address, (e) output means responsive to the output of said selection means for providing outputs of said flip-flops, and (f) transfer means for transferring the outputs from said output means to said scan-out control means to allow read-out of the states of the designated flip-flop circuits through said panel.

Claim 8

A data processing apparatus comprising logic circuits with flip-flop circuits therein and a self-diagnosis circuit for effecting self-diagnosis of internal states of the data processing apparatus while the data processing apparatus is in the course of operation, said self-diagnosis circuit comprising: (a) scan-out control means coupled to a microprocessor and a maintenance panel to generate a first scan-out address which designates one of groups of said flip-flop circuits and adapted to receive scan-out data from the flip-flop circuits of the group designated by said first scan-out address, (b) address generating circuits supplied with said first scan-out address for generating second scan-out addresses bit by bit for the flip-flop circuits of the group designated by said first scan-out address in sequence, (c) a maintenance scan address register settable by said maintenance panel and constantly generating a bit address which designates a specified one of said flip-flop circuits, (d) selection means for selecting one of said second scan-out addresses and said bit address, (e) output means responsive to the output of said selection means for providing outputs of said flip-flops, and (f) transfer means for transferring the outputs from said output means to said scan-out control means to allow read-out of the states of the designated flip-flop circuits through said panel.

Claim 9

The apparatus according to claim 6 further comprising an observing means coupled to said transfer means for observing the outputs from said output means.

Claim 10

The apparatus according to claim 6, wherein said selection means is operative to select the bit address from the maintenance scan address register only during periods when the scan-out control means is inoperative.

Claim 11

The apparatus according to claim 8, wherein said selection means repeatedly selects said bit address during periods in which the scan-out control means is inoperative so that said transfer means can provide read-outs through said panel to permit continually monitoring the state of the flip-flop designated by said bit address.