Clock phase discriminator

Claim 2

A phase discriminator, responsive to the difference in phase between an input clock signal and a variable-frequency reference clock signal, for producing phase correction signals that are used to change the frequency of said reference clock signal, comprising: means responsive to an input clock signal for producing a start cycle signal; latch circuit means, responsive to a transistion of a reference clock signal following said start cycle signal and to an input clock signal transistion following said start cycle signal for measuring a phase difference between said input and reference clock signals by producing and changing variable signals defining a multi-state transition cycle, in which each state transition results from the change of a single respective variable signal, and for producing phase difference signals indicative of the measured phase difference; and gate means responsive to said phase difference signals for producing a phase correction signal to change the frequency of said reference clock signal to a frequency that reduces said phase difference.

Claim 3

The phase discriminator of claim 1 wherein said phase difference signals further indicate which of said clock signal transitions occurred first.

Claim 4

The phase discriminator of claim 1 wherein said latch circuit means includes plural binary latches, each binary latch having an input connected to the output of at least one other binary latch and changing state in response to the change of output of only a respective one of said other binary latches.

Claim 5

The phase discriminator of claim 3 wherein one said binary latch comprises a differential, emitter-coupled circuit.

Claim 6

The apparatus of claim 4 wherein said latch includes a differential emitter-coupled circuit with a signal output network comprising: a resistance ladder including a plurality of series-connected resistors, in which respective outputs of said latch are provided from connection nodes within and at either end of said series-connected resistors; and an output signal voltage-determining leg in parallel with said resistance ladder network and including, in series, a semiconductor element having a predetermined forward bias voltage and a resistance element, in which the combined signal voltage drop across said leg maintains the respective output signal voltage at each node paralleled by said leg at or above a predetermined level.

Claim 7

A phase measurement apparatus, comprising: start latch means responsive to an input clock signal of nomial frequency for producing a start cycle signal; divider means responsive to said start cycle signal and to a variable-frequency reference clock signal for producing a comparison clock signal having substantially the same frequency as said input clock signal; phase measurement cycle means responsive to a comparison clock signal transition following said start cycle signal signal and to an input clock transition following said start cycle signal for measuring a phase difference between said input and reference clock signals by producing a plurality of variable signals and changing said variable signals according to a predetermined pattern defining a multi-state phase-measurement cycle in which each state transition results from the change of a single respective variable signal; and gate means responsive to said phase measurement cycle means for producing correction signals to change the frequency of said reference clock signal by an amount that reduces said measured phase difference.

Claim 8

A phase measurement apparatus, comprising: start latch means responsive to an input clock signal of nomial frequency for producing a start cycle signal; divider means responsive to said start cycle signal and to a variable-frequency reference clock signal for producing a comparison clock signal having substantially the same frequency as said input clock signal; phase measurement cycle means responsive to a comparison clock signal transition following said start cycle signal signal and to an input clock transition following said start cycle signal for measuring a phase difference between said input and reference clock signals by producing a plurality of variable signals and changing said variable signals according to a predetermined pattern defining a multi-state phase-measurement cycle in which each state transition results from the change of a single respective variable signal; and gate means responsive to said phase measurement cycle means for producing correction signals to change the frequency of said reference clock signal by an amount that reduces said measured phase difference.

Claim 9

The apparatus of claim 6 wherein, if said comparison clock transition precedes said input clock transition, said phase measurement cycle means produces a first phase difference signal for a time corresponding to the time separating said clock signal transitions or, if said input clock transition precedes said comparison clock transition, said phase measurement cycle means produces a second phase difference signal for a time corresponding to the time separating said clock signal transitions.

Claim 10

The apparatus of claim 7 wherein said gate means responds to said first phase difference signal by producing a decrease correction signal to decrease said reference clock signal frequency or to said second phase difference signal by producing an increase correction signal to increase said reference clock signal frequency.

Claim 11

The apparatus of claim 6 wherein said predetermined pattern comprises two complementary multistate transition cycles in each of which at least one state is the complement of a respective state in the other.

Claim 12

The apparatus of claim 9 wherein each of said transition cycles includes an initial and an ending state, and the initial state of each of said cycles comprises the ending state of the other of said cycles.

Claim 13

The apparatus of claim 6 wherein said phase measurement cycle means includes plural binary latches, each of said latches having an output corresponding to a respective variable signal and an input connected to receive the output of at least one other of said binary latches, and wherein each of said latches changes its output in response to the change in output of only one of the others of said latches.