US3701039A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Random binary data signal frequency and phase compensation circuit
Assignee: International Business Machines Corp
•
Filing: 1968-10-28
•
Granted: 1972-10-24
•
Expires: 1988-10-28
Abstract
Abstract A phase lock oscillator includes a phase discriminator that develops an error signal by comparing a clock from a voltage controlled oscillator with incoming random data bits. In the absence of data, the phase lock oscillator is inactive. However, when data is sensed, a logic and delay network in the phase discriminator develops an error voltage of suitable polarity and amplitude, indicative of the lead or lag between the data and clock signals. The error voltage is applied to the voltage controlled oscillator to modify the frequency and phase of the clock. Furthermore, first and second integrations are provided by the phase discriminator and an integrator respectively so that the steady state phase error is held close to zero.
Inventors
- 👤 Paul C Lang
- 👤 Anthony N La Pine
- 👤 Julian E Vaughn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 10:46
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/089; H03L7/0891; H03D; H03D13/00; H03D13/003; H03D13/004
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
163 words
A signal phase compensation circuit for processing random data comprising: a voltage controlled oscillator for providing a timing signal having a nominal frequency related to the frequency of an incoming random data signal; means for detecting the phase of such incoming random data signal and for comparing said detected phase to the phase of the timing signal to produce a phase error signal, said detecting means being inactive in the absence of input data; means coupled to said detecting means for transforming said phase error signal to an electric current; an integrating circuit for developing an error voltage in response to said electric current; said voltage controlled oscillator being coupled between said integrating circuit and said detecting means; said detecting means comprising a digital phase discriminator having first and second channels for respectively increasing and decreasing the frequency of said voltage controlled oscillator, said first and second channels including delays for allowing said phase compensation circuit to operate outside of dead zone areas.
Claim 2
Dependent Claim
163 words
A signal phase compensation circuit for processing random data comprising: a voltage controlled oscillator for providing a timing signal having a nominal frequency related to the frequency of an incoming random data signal; means for detecting the phase of such incoming random data signal and for comparing said detected phase to the phase of the timing signal to produce a phase error signal, said detecting means being inactive in the absence of input data; means coupled to said detecting means for transforming said phase error signal to an electric current; an integrating circuit for developing an error voltage in response to said electric current; said voltage controlled oscillator being coupled between said integrating circuit and said detecting means; said detecting means comprising a digital phase discriminator having first and second channels for respectively increasing and decreasing the frequency of said voltage controlled oscillator, said first and second channels including delays for allowing said phase compensation circuit to operate outside of dead zone areas.
Claim 3
Dependent Claim
150 words
A signal phase compensation circuit for processing random data comprising: a voltage controlled oscillator for providing a timing signal having a nominal frequency related to the frequency of an incoming random data signal; means for detecting the phase of such incoming random data signal and for comparing said detected phase to the phase of the timing signal to produce a phase error signal, said detecting means being inactive in the absence of input data; means coupled to said detecting means for transforming said phase error signal to an electric current; an integrating circuit for developing an error voltage in response to said electric current; said voltage controlled oscillator being coupled between said integrating circuit and said detecting means; said detecting means comprising a digital phase discriminator that includes a bistable multivibrator, which is set in response to said random data signal, and is reset in response to said timing signal.
Claim 4
Dependent Claim
150 words
A signal phase compensation circuit for processing random data comprising: a voltage controlled oscillator for providing a timing signal having a nominal frequency related to the frequency of an incoming random data signal; means for detecting the phase of such incoming random data signal and for comparing said detected phase to the phase of the timing signal to produce a phase error signal, said detecting means being inactive in the absence of input data; means coupled to said detecting means for transforming said phase error signal to an electric current; an integrating circuit for developing an error voltage in response to said electric current; said voltage controlled oscillator being coupled between said integrating circuit and said detecting means; said detecting means comprising a digital phase discriminator that includes a bistable multivibrator, which is set in response to said random data signal, and is reset in response to said timing signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-24 | 1976-04-24 | 1976-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-24 | 1980-04-24 | 1980-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-24 | 1984-04-24 | 1984-10-24 | $7700.00 | Window Closed / Lapsed |