Patent US4697103A successfully refreshed from Google Patents.
US4697103A
Expired / Lapsed
US
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Low power high current sinking TTL circuit
Assignee: Quadic Systems Inc
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Filing: 1986-03-10
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Granted: 1987-09-29
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Expires: 2006-03-10
Abstract
Abstract A multi-terminal transistor circuit structure is described for TTL applications including current sinking and "pull-down" transistor circuit elements. A transistor pair is coupled with the emitter of the second transistor coupled to the base of the first transistor. The collector and emitter of the first transistor provide first and second terminals and the bases of the transistor pair provide independent third and fourth terminals or current controlled inputs. The new circuit structure is incorporated in a tranistor transistor logic (TTL) output buffer circuit and provides first and second pull-down transistor elements having the emitter of the second transistor coupled to the base of the first pull-down transistor. An independent base drive is coupled to the base of the second pull-down transistor element. The second stage pull-down transistor element introduces full square law enhancement of β 2 amplification of the output sinking current in a high current sinking mode while eliminating prior art feedback diodes and dual phase splitter transistors. The separate input and base drive coupling to the base of the additional pull-down avoids "current hogging" of the base drive by the phase splitter transistor. The circuit is applicable in both TTL bistate and tristate devices and is characterized by low power dissipation, low output impedance and high current sinking capability.
Inventors
- 👤 David A. Ferris
- 👤 Daniel J. DeSimone
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 00:58
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/0823; H03K19/0826; H03K19/0008; H03K19/001; H03K19/01; H03K19/013; H03K19/0136
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
231 words
An improved TTL output buffer circuit for digital data transmission comprising: a signal input for receiving binary data signals of high or low potential; a signal output for delivering binary data signals of low or high potential in response to binary data signals at the input; a pull-up transistor element for sourcing current from high potential (V cc ) to the signal output; a first pull-down transistor element for sinking current from the signal output to low potential; a phase splitter transistor element having an emitter coupled to the base of the first pull-down transistor element for controlling the conducting state of the first pull-down transistor element, said phase splitter transistor element having a collector coupled to the base of said pull-up transistor element; first base drive means coupling the base of the phase splitter transistor element to the signal input; a second pull-down transistor element having the collector coupled to the collector of the first pull-down transistor element at the signal output and the emitter coupled to drive the base of the first pull-down transistor element for square law enhancement and amplification of sinking current by the first pull-down transistor element; and second base drive means coupling the base of the second pull-down transistor element to the signal input for providing base drive independent from the first base drive means in response to binary data signals at the signal input.
Claim 2
Dependent Claim
231 words
An improved TTL output buffer circuit for digital data transmission comprising: a signal input for receiving binary data signals of high or low potential; a signal output for delivering binary data signals of low or high potential in response to binary data signals at the input; a pull-up transistor element for sourcing current from high potential (V cc ) to the signal output; a first pull-down transistor element for sinking current from the signal output to low potential; a phase splitter transistor element having an emitter coupled to the base of the first pull-down transistor element for controlling the conducting state of the first pull-down transistor element, said phase splitter transistor element having a collector coupled to the base of said pull-up transistor element; first base drive means coupling the base of the phase splitter transistor element to the signal input; a second pull-down transistor element having the collector coupled to the collector of the first pull-down transistor element at the signal output and the emitter coupled to drive the base of the first pull-down transistor element for square law enhancement and amplification of sinking current by the first pull-down transistor element; and second base drive means coupling the base of the second pull-down transistor element to the signal input for providing base drive independent from the first base drive means in response to binary data signals at the signal input.
Claim 3
Dependent Claim
41 words
The TTL output buffer circuit of claim 1 comprising an enable input circuit element coupled to the base of the phase splitter transistor element and to the base of the second pull-down transistor element to enable a high impedance third state.
Claim 4
Dependent Claim
21 words
The TTL output buffer circuit of claim 2 wherein the phase splitter transistor element consists of a single phase splitter transistor.
Claim 5
Dependent Claim
41 words
The TTL output buffer circuit of claim 1 further comprising a sinking current set transistor element having the base coupled to the signal output, collector coupled to the base of the second pull-down transistor element and emitter coupled to low potential.
Claim 6
Dependent Claim
204 words
A TTL output circuit for digital data transmission comprising: a signal input for receiving binary data signals of low or high potential; a signal output for delivering binary data signals of high or low potential; a first pull-down transistor element for sinking current from the signal output to low potential; a pull-up transistor element for sourcing current from high potential (V ee ) to the signal output; a phase splitter transistor element having an emitter coupled to the base of the first pull-down transistor element for controlling the conducting state of the first pull-down transistor element, said phase splitter transistor element having a collector coupled to the base of said pull-up transistor element; first base drive means coupling the base of the phase splitter transistor element to the signal input; a second pull-down transistor element having an emitter coupled to drive the base of the first pull-down transistor element for square law enhancement and amplification of sinking current by the first pull-down transistor element; and second independent base drive means coupling the base of the second pull-down transistor element to the signal input for providing base drive independent from the first base drive means in response to binary data signals at the signal input.
Claim 7
Dependent Claim
204 words
A TTL output circuit for digital data transmission comprising: a signal input for receiving binary data signals of low or high potential; a signal output for delivering binary data signals of high or low potential; a first pull-down transistor element for sinking current from the signal output to low potential; a pull-up transistor element for sourcing current from high potential (V ee ) to the signal output; a phase splitter transistor element having an emitter coupled to the base of the first pull-down transistor element for controlling the conducting state of the first pull-down transistor element, said phase splitter transistor element having a collector coupled to the base of said pull-up transistor element; first base drive means coupling the base of the phase splitter transistor element to the signal input; a second pull-down transistor element having an emitter coupled to drive the base of the first pull-down transistor element for square law enhancement and amplification of sinking current by the first pull-down transistor element; and second independent base drive means coupling the base of the second pull-down transistor element to the signal input for providing base drive independent from the first base drive means in response to binary data signals at the signal input.
Claim 8
Dependent Claim
38 words
The TTL output circuit of claim 5 comprising an enable input coupled to the base of the phase splitter transistor element and to the base of the second pull-down transistor element to enable a high impedance third state.
Claim 9
Dependent Claim
19 words
The TTL output circuit of claim 6 wherein the phase splitter transistor element consists of single phase splitter transistor.
Claim 10
Dependent Claim
25 words
The TTL output circuit of claim 5 wherein the collector of the second pull-down transistor element (Q21) is independently coupled to high potential (V ).
Claim 11
Dependent Claim
19 words
The TTL output circuit of claim 8 wherein the second pull-down transistor element (Q21) is coupled in emitter-follower configuration.
Claim 12
Dependent Claim
65 words
The TTL output circuit of claim 8 further comprising a diode (Dl) coupled between the base of the second pull-down transistor element (Q21) and the collector of the first pull-down transistor element (Q22) said diode (D1) having a low resistance conducting direction oriented to conduct from the base of the second pull-down transistor element (Q21) to the collector of the first pull-down transistor element (Q22).
Claim 13
Dependent Claim
33 words
The TTL output circuit of claim 5 wherein the collector of the second pull-down transistor element (Q5) is coupled to the collector of the first pull-down transistor element (Q3) at the signal output.
Claim 14
Dependent Claim
141 words
A multi-terminal transistor circuit comprising: first and second transistors, the emitter of the second transistor being coupled to drive the base of the first transistor for square law enhancement and amplification of current by the first transistor, the collector of the first transistor comprising a first terminal, the emitter of the first transistor comprising a second terminal, and the bases of the first and second transistors comprising independent base drive third and fourth terminals, the collector of the second transistor being coupled to a source of high potential (V cc ) in emitter-follower configuration, and a diode coupled between the base of the second transistor and the collector of the first transistor said diode having a low resistance conducting direction oriented to conduct from the base of the second pull-down transistor element to the collector of the first pull-down transistor element.
Claim 15
Dependent Claim
141 words
A multi-terminal transistor circuit comprising: first and second transistors, the emitter of the second transistor being coupled to drive the base of the first transistor for square law enhancement and amplification of current by the first transistor, the collector of the first transistor comprising a first terminal, the emitter of the first transistor comprising a second terminal, and the bases of the first and second transistors comprising independent base drive third and fourth terminals, the collector of the second transistor being coupled to a source of high potential (V cc ) in emitter-follower configuration, and a diode coupled between the base of the second transistor and the collector of the first transistor said diode having a low resistance conducting direction oriented to conduct from the base of the second pull-down transistor element to the collector of the first pull-down transistor element.
Claim 16
Dependent Claim
31 words
The circuit of claim 4 further comprising first and second independent base drive means coupled respectively to the bases of the first and second transistors at the third and fourth terminals.
Claim 17
Dependent Claim
31 words
The circuit of claim 12 further comprising first and second independent base drive means coupled respectively to the bases of the first and second transistors at the third and fourth terminals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-09-28 | 1991-03-30 | 1991-09-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-09-28 | 1995-03-30 | 1995-09-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-09-28 | 1999-03-30 | 1999-09-29 | $7700.00 | Window Closed / Lapsed |