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US4696016A
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US
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Digital clock recovery circuit for return to zero data
Assignee: Rockwell Firstpoint Contact Corp
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Filing: 1986-10-02
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Granted: 1987-09-22
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Expires: 2006-10-02
Abstract
Abstract A digital clock recovery circuit is described which extracts the signal element timing from a return-to-zero data stream. A converter changes the bipolar digital data stream to at least one first return-to-zero data stream representing pulses in the bipolar digital data stream. In these streams, a logic one is typically represented by a pulse of undetermined width less than the bit period. A logic zero is typically represented by no pulse. A reference clock signal having a predetermined frequency is required by the circuitry. An edge detector detects the positive going edges of the pulses in the combined return-to-zero data stream, and generates load pulses to a counter which are synchronized to transitions of the reference clock signal. The counter receives the load pulses and utilizes reference clock signal to produce a recovered clock signal, skiping or repeating counter states to kepp the recovered clock signal aligned with the bipolar digital data stream.
Inventors
- 👤 John G. Rozema
- 👤 Kenneth A. Thompson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:30
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0331
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
172 words
A data-rate clock pulse recovery circuit for use with a bipolar digital data stream comprising: means for providing a refernce clock signal having a predetermined frequency; means for converting the bipolar data stream to a first return-to-zero data stream representing the positive going pulses in the bipolar data stream and to a second return-to-zero data stream representing the negative pulses in the bipolar data stream; means for combining said first and second return-to-zero data streams to form a combined return-to-zero data stream; means for detecting the next positive going edge of said reference clock signal after detecting the positive going edge of the pulse of said combined return-to-zero data stream, said means for detecting, receiving said combined return-to-zero data stream and said reference clock signal and producing an edge detected data stream; means for counting, receiving said edge detected data stream and said reference clock signal to produce a recovered clock signal; wherein said means for counting skips or repeats a state when the phase of said combined return-to-zero data stream drifts.
Claim 2
Dependent Claim
172 words
A data-rate clock pulse recovery circuit for use with a bipolar digital data stream comprising: means for providing a refernce clock signal having a predetermined frequency; means for converting the bipolar data stream to a first return-to-zero data stream representing the positive going pulses in the bipolar data stream and to a second return-to-zero data stream representing the negative pulses in the bipolar data stream; means for combining said first and second return-to-zero data streams to form a combined return-to-zero data stream; means for detecting the next positive going edge of said reference clock signal after detecting the positive going edge of the pulse of said combined return-to-zero data stream, said means for detecting, receiving said combined return-to-zero data stream and said reference clock signal and producing an edge detected data stream; means for counting, receiving said edge detected data stream and said reference clock signal to produce a recovered clock signal; wherein said means for counting skips or repeats a state when the phase of said combined return-to-zero data stream drifts.
Claim 3
Dependent Claim
38 words
The apparatus defined in claim 1 wherein said data-rate clock pulse recovery circuit further comprises: means for providing a predetermined time delay connected to an output of said means for counting to produce a time-delayed recovered clock signal.
Claim 4
Dependent Claim
95 words
The apparatus defined in claim 1 wherein said data-rate clock pulse recovery circuit further comprises: first means for retiming receiving said reference clock signal, said recovered clock signal and said first return-to-zero data stream to produce a retimed first non-return-to-zero data stream which is synchronized to said recovered clock signal and wherein said data-rate clock pulse recovery circuit also comprises second means for retiming receiving said pulse clock signal, said recovered clock signal and said second return-to-zero data stream to produce a retimed second non-return-to-zero data stream which is synchronized to said recovered clock signal.
Claim 5
Dependent Claim
262 words
A data-rate clock pulse recovery circuit for use with a bipolar digital data stream comprising: means for converting a bipolar digital data stream to a first return-to-zero data stream representing the positive going pulses in the bipolar digital data stream and to a second return-to-zero data stream representing the negative pulses in the bipolar digital data stream; means for providing a reference clock signal having predetermined frequency; means for combining said first and second return-to-zero data streams to form a combined return-to-zero data stream; means for detecting the next positive going edge of said reference clock signal after detecting the positive going edge of a pulse of said combined return-to-zero data stream, said means for detecting, receiving said combined return-to-zero data stream and said reference clock signal and producing an edge detected data stream; means for counting receiving said edge detected data stream and said pulse clock signal to produce a recovered clock signal; first means for retiming, receiving said reference clock signal, said recovered clock signal and said first return-to-zero data stream to produce a retimed first non-return-to-zero data stream which is synchronized to said recovered clock signal; and second means for retiming receiving said reference clock signal, said recovered clock signal and said second return-to-zero data stream to produce a retimed second non-return-to-zero data stream which is synchronized to said recovered clock signal wherein said means for counting skips or repeats a state when the phase of said combined return-to-zero data stream drifts thereby keeping said recovered clock signal aligned with said retained retimed first and second non-return-to-zero data streams.
Claim 6
Dependent Claim
262 words
A data-rate clock pulse recovery circuit for use with a bipolar digital data stream comprising: means for converting a bipolar digital data stream to a first return-to-zero data stream representing the positive going pulses in the bipolar digital data stream and to a second return-to-zero data stream representing the negative pulses in the bipolar digital data stream; means for providing a reference clock signal having predetermined frequency; means for combining said first and second return-to-zero data streams to form a combined return-to-zero data stream; means for detecting the next positive going edge of said reference clock signal after detecting the positive going edge of a pulse of said combined return-to-zero data stream, said means for detecting, receiving said combined return-to-zero data stream and said reference clock signal and producing an edge detected data stream; means for counting receiving said edge detected data stream and said pulse clock signal to produce a recovered clock signal; first means for retiming, receiving said reference clock signal, said recovered clock signal and said first return-to-zero data stream to produce a retimed first non-return-to-zero data stream which is synchronized to said recovered clock signal; and second means for retiming receiving said reference clock signal, said recovered clock signal and said second return-to-zero data stream to produce a retimed second non-return-to-zero data stream which is synchronized to said recovered clock signal wherein said means for counting skips or repeats a state when the phase of said combined return-to-zero data stream drifts thereby keeping said recovered clock signal aligned with said retained retimed first and second non-return-to-zero data streams.
Claim 7
Dependent Claim
37 words
The apparatus described in claim 4 wherein said data-rate clock pulse recovery circuit further comprises means for providing predetermined timed delay connected to an output of said means for counting to produce a time-delayed recovered clock signal.
Claim 8
Independent Claim
165 words
A method of providing data-rate clock pulse recovery for use with a bipolar digital data stream comprising: converting the bipolar digital data stream to a first return-to-zero data stream representing the positive going pulses in the bipolar digital data stream and to a second return-to-zero data stream representing the negative pulses in the bipolar digital data stream; providing a reference clock signal having a predetermined frequency; combining said first and second return-to-zero data streams to form a combined return-to-zero data stream; detecting the next positive going edge of said reference clock signal after detecting the positive going edge of a pulse of said combined return-to-zero data stream, said means for detecting receiving said combined return-to-zero data stream and said reference clock signal producing an edge detected data stream; and counting said received edge detected data stream in said pulse clock signal to produce a recovered clock signal wherein said counting skips ro repeats a state when the phase of said combined return-to-zero data stream drifts.
Claim 9
Independent Claim
165 words
A method of providing data-rate clock pulse recovery for use with a bipolar digital data stream comprising: converting the bipolar digital data stream to a first return-to-zero data stream representing the positive going pulses in the bipolar digital data stream and to a second return-to-zero data stream representing the negative pulses in the bipolar digital data stream; providing a reference clock signal having a predetermined frequency; combining said first and second return-to-zero data streams to form a combined return-to-zero data stream; detecting the next positive going edge of said reference clock signal after detecting the positive going edge of a pulse of said combined return-to-zero data stream, said means for detecting receiving said combined return-to-zero data stream and said reference clock signal producing an edge detected data stream; and counting said received edge detected data stream in said pulse clock signal to produce a recovered clock signal wherein said counting skips ro repeats a state when the phase of said combined return-to-zero data stream drifts.
Claim 10
Dependent Claim
28 words
The method defined in claim 6 wherein said method further comprises providing a predetermined time delay to said recovered clock signal to produce a time-delayed recovered clock signal.
Claim 11
Dependent Claim
42 words
The method defined in claim 6 wherein said method further comprises retiming said reference clock signal, said recovered clock signal and said first return-to-zero data stream to produce a retimed first non-return-to-zero data stream which is synchronized to said recovered clock signal.
Claim 12
Dependent Claim
42 words
The method defined in claim 6 wherein said method further comprises retiming said reference clock signal, said recovered clock signal and said second return-to-zero data stream to produce a retimed second non-return-to-zero data stream which is synchronized to said recovered clock signal.
Claim 13
Dependent Claim
136 words
A data-rate clock pulse recovery circuit for use with a bipolar digital data stream comprising: means for providing a reference clock signal having a predetermined frequency; means for converting the bipolar data stream to at least one return-to-zero data stream representing the pulses in the bipolar data stream; means for detecting the next positive going edge of said reference clock signal after detecting a positive going edge of the pulse of said return-to-zero data stream, said means for detecting, receiving said return-to-zero data stream and said reference clock signal and producing an edge detected data stream; and means for counting, receiving said edge detected data stream and said reference clock signal to produce a recovered clock signal; wherein said means for counting skips or repeats a state when the phase of said return-to-zero data stream drifts.
Claim 14
Dependent Claim
136 words
A data-rate clock pulse recovery circuit for use with a bipolar digital data stream comprising: means for providing a reference clock signal having a predetermined frequency; means for converting the bipolar data stream to at least one return-to-zero data stream representing the pulses in the bipolar data stream; means for detecting the next positive going edge of said reference clock signal after detecting a positive going edge of the pulse of said return-to-zero data stream, said means for detecting, receiving said return-to-zero data stream and said reference clock signal and producing an edge detected data stream; and means for counting, receiving said edge detected data stream and said reference clock signal to produce a recovered clock signal; wherein said means for counting skips or repeats a state when the phase of said return-to-zero data stream drifts.
Claim 15
Dependent Claim
51 words
The apparatus defined in claim 10 wherein said data rate clock pulse recovery circuit further comprises: at least one means for retiming, receiving said reference clock signal, said recovered clock signal and said return-to-zero data stream to produce a retimed non-return-to-zero data stream which is synchronized to said recovered clock signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-09-21 | 1991-03-23 | 1991-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-09-21 | 1995-03-23 | 1995-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-09-21 | 1999-03-23 | 1999-09-22 | $7700.00 | Window Closed / Lapsed |