Patent US4695753A successfully refreshed from Google Patents.
US4695753A
Expired / Lapsed
US
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Charge sensor having a preset flipflop
Assignee: US Philips Corp
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Filing: 1986-09-18
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Granted: 1987-09-22
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Expires: 2006-09-18
Abstract
Abstract The invention relates to a charge detector, more particularly for reading binary information in a CTD. The detector includes a flipflop having two cross-coupled MOS transistors and two MOS transistors acting as loads. The signal to be read and the reference signal are supplied to the gates of the loads. The junctions between the driver transistors and the loads are connected to reset transistors. The drains of the loads are applied to a (fixed) supply voltage and the sources of the driver transistors are applied via a switching transistor to the supply voltage return. The circuit arrangement is operated so that before the activation of the flipflop the said junctions are set to a signal-dependent preadjustment. When the switching transistor is then energized, the flipflop will be in the correct stage with a higher degree of reliability and without being influenced by clock cross-talk.
Inventors
- 👤 Marcellinus J. M. Pelgrom
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 20:47
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/28; G11C19/282; G11C19/285
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
486 words
A charge sensor, for use with a charge transfer device comprising: two cross-coupled MOS transistors T 1 and T 2 each having a source, a drain and a gate, the gate of T 2 and the drain of T 1 being connected to a first junction A 1 and the gate of T 1 and the drain of T 2 being connected to a second junction A 2 , while the sources of T 1 and T 2 are connected to a third junction A 3 ; two load MOS transistors T 3 and T 4 each having a source, a drain and a gate, the sources of T 3 and T 4 being directly and continuously connected to A 1 and A 2 , respectively, and the drains of T 3 and T 4 being directly and continuously connected to a fourth junction A 4 , while the gates of T 3 and T 4 are coupled to a signal supply means; a positive and negative current supply lead for passing a current between the junctions A 3 and A 4 , junction A 4 being directly and continuously connected to one of said current supply leads, and a fifth MOS transistor T 5 , which acts as a switch and has a gate which is connected to a clock voltage source which also timely applies the clock voltage for the intermittent energization of the sensor, a source and a drain; a sixth (T 6 ) and a seventh (T 7 ) MOS transistor, each having a source, a drain and a gate, the drain of T 6 being connected to A 1 and the drain of T 7 being connected to A 2 , while the sources of T 6 and T 7 are connected to the other of the current supply leads and the gates are connected to a clock voltage source for intermittently opening and closing the transistors T 6 and T 7 ; the drain of T 5 being connected to the junction A 3 and the source of T 5 being directly and continuously connected to the other supply lead associated with A 3 and the gates of T 5 , T 6 and T 7 being connected to said clock voltage sources which supply clock voltage in a manner such that at the beginning of each cycle the junctions A 1 and A 2 are first set to a rest voltage by closing the transistors T 6 and T 7 , after which, while T 5 is opened, T 6 and T 7 are also opened and the signal charges to be read are supplied directly to the gates of T 3 and T 4 , as a result of which a signal-dependent voltage difference is obtained between the junctions A 1 and A 2 , whereupon the transistors T 5 is closed and said voltage difference is increased.
Claim 2
Dependent Claim
486 words
A charge sensor, for use with a charge transfer device comprising: two cross-coupled MOS transistors T 1 and T 2 each having a source, a drain and a gate, the gate of T 2 and the drain of T 1 being connected to a first junction A 1 and the gate of T 1 and the drain of T 2 being connected to a second junction A 2 , while the sources of T 1 and T 2 are connected to a third junction A 3 ; two load MOS transistors T 3 and T 4 each having a source, a drain and a gate, the sources of T 3 and T 4 being directly and continuously connected to A 1 and A 2 , respectively, and the drains of T 3 and T 4 being directly and continuously connected to a fourth junction A 4 , while the gates of T 3 and T 4 are coupled to a signal supply means; a positive and negative current supply lead for passing a current between the junctions A 3 and A 4 , junction A 4 being directly and continuously connected to one of said current supply leads, and a fifth MOS transistor T 5 , which acts as a switch and has a gate which is connected to a clock voltage source which also timely applies the clock voltage for the intermittent energization of the sensor, a source and a drain; a sixth (T 6 ) and a seventh (T 7 ) MOS transistor, each having a source, a drain and a gate, the drain of T 6 being connected to A 1 and the drain of T 7 being connected to A 2 , while the sources of T 6 and T 7 are connected to the other of the current supply leads and the gates are connected to a clock voltage source for intermittently opening and closing the transistors T 6 and T 7 ; the drain of T 5 being connected to the junction A 3 and the source of T 5 being directly and continuously connected to the other supply lead associated with A 3 and the gates of T 5 , T 6 and T 7 being connected to said clock voltage sources which supply clock voltage in a manner such that at the beginning of each cycle the junctions A 1 and A 2 are first set to a rest voltage by closing the transistors T 6 and T 7 , after which, while T 5 is opened, T 6 and T 7 are also opened and the signal charges to be read are supplied directly to the gates of T 3 and T 4 , as a result of which a signal-dependent voltage difference is obtained between the junctions A 1 and A 2 , whereupon the transistors T 5 is closed and said voltage difference is increased.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-09-21 | 1991-03-23 | 1991-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-09-21 | 1995-03-23 | 1995-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-09-21 | 1999-03-23 | 1999-09-22 | $7700.00 | Window Closed / Lapsed |