US4692783A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gate array
Assignee: Fujitsu Ltd
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Filing: 1986-10-23
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Granted: 1987-09-08
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Expires: 2006-10-23
Abstract
Abstract A gate array is disclosed having a plurality of basic cells each comprising a transistor whose gm is as low as one fifth to one twentieth that of the transistors in a conventional gate array. The low gm is provided by reducing the W/L ratio of the gate region of the transistor. The basic cell having the transistor of the low gm is formed to replace the conventional basic cell at a specified position in a specified basic cell array. The transistor of low gm reduces the number of basic cells necessary for forming a delay circuit, and elminates the need for an external resistance component which was formerly required when a pull-up or pull-down circuit or a monostable multivibrator was formed in the gate array.
Inventors
- 👤 Hideo Monma
- 👤 Masato Ishiguro
- 👤 Tetsuo Kawano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 12:07
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0158; H10D84/0165; H10D84/0193
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
228 words
A basic cell including a plurality of transistors formed in a semiconductor substrate, said basic cell comprising: a first p-channel MIS (Metal-Insulator-Semiconductor) transistor and a first n-channel transistor having a first single common gate electrode, a second p-channel MIS transistor and a second n-channel MIS transistor having a second single common gate electrode, said first and second gate electrodes being of substantially the same length and extending parallel to each other in close proximity; said first p-channel and n-channel transistors having source or drain regions with a gate portion conduction channel of width W formed near opposite ends of said first common gate electrode, a portion of each said source or drain region extending toward the other along said gate electrode at a side opposited to said second common gate electrode; said second p-channel and n-channel transistors having source or drain regions with a gate portion conduction channel of width W formed apart from each other near the center of said second common gate electrode, a portion of each said source or drain region extending away from the other along said gate electrode at a side opposite to said first common gate electrode; said first and second gate electrodes being broadened in width at each gate portion thereof to provide a gate portion conduction channel of length L whereby a specified W/L ratio is attained in each transistor.
Claim 2
Dependent Claim
228 words
A basic cell including a plurality of transistors formed in a semiconductor substrate, said basic cell comprising: a first p-channel MIS (Metal-Insulator-Semiconductor) transistor and a first n-channel transistor having a first single common gate electrode, a second p-channel MIS transistor and a second n-channel MIS transistor having a second single common gate electrode, said first and second gate electrodes being of substantially the same length and extending parallel to each other in close proximity; said first p-channel and n-channel transistors having source or drain regions with a gate portion conduction channel of width W formed near opposite ends of said first common gate electrode, a portion of each said source or drain region extending toward the other along said gate electrode at a side opposited to said second common gate electrode; said second p-channel and n-channel transistors having source or drain regions with a gate portion conduction channel of width W formed apart from each other near the center of said second common gate electrode, a portion of each said source or drain region extending away from the other along said gate electrode at a side opposite to said first common gate electrode; said first and second gate electrodes being broadened in width at each gate portion thereof to provide a gate portion conduction channel of length L whereby a specified W/L ratio is attained in each transistor.
Claim 3
Dependent Claim
39 words
A basic cell as recited in claim 1 wherein said first gate electrode is narrow at a central portion between said gate portions thereof, and said second gate electrode is narrow at end portions outside said gate portions thereof.
Claim 4
Dependent Claim
28 words
A basic cell as recited in claim 2 wherein said first and second gate electrode broadened and narrow portions, respectively, are alternately staggered in the longitudinal direction thereof.
Claim 5
Dependent Claim
19 words
A basic cell as recited in claim 1 wherein said specified W/L ratio is the same in each transistor.
Claim 6
Dependent Claim
18 words
A basic cell as recited in claim 1 wherein said specified W/L ration is different in each transistor.
Claim 7
Dependent Claim
111 words
A basic cell as recited in claim 1 wherein the drains of said first p-channel transistor and said first n-channel transistor are each connected to said second gate electrode, the sources of said first and second p-channel transistors are each connected to a positive potential source, the sources of said first and second n-channel transistors are each connected to a negative potential source, a connection is provided to said first gate electrode to from an input connection, and the drains of the said second p-channel transistor and said second n-channel transistor are connected together to form an output connection, thereby constituting a double-staged inverter circuit which functions as a buffer circuit.
References Cited (Backward Citations)
US3508084A
Cited
US4278897A
Cited
JPS57133712A
Cited
EP0058504A2
Cited
JPS5851536A
Cited
JPS58139446A
Cited
US4575745A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-09-07 | 1991-03-09 | 1991-09-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-09-07 | 1995-03-09 | 1995-09-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-09-07 | 1999-03-09 | 1999-09-08 | $7700.00 | Window Closed / Lapsed |