EP0058504A2
Expired / Lapsed
EP
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Method of constructing a delay circuit in a master slice IC
Assignee: Fujitsu Ltd
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Filing: 1982-02-09
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Granted: —
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Expires: 2002-02-09
Abstract
Abstract In a method of constructing a delay circuit in a master slice IC formed on a semiconductor substrate, the master slice IC comprises regularly arranged MIS transistors (Qn, Qp) having gate electrodes (61-66). The MIS transistors constitute various logic circuits. A delay circuit (DLY) is formed between two logic circuits (INV1, INV2) and comprises resistance and capacitance. The resistance is formed by the resistances of the gate electrodes by connecting sequentially (L6-L10) the gate electrodes (62-65) between the two logic circuits. The capacitor is formed by capacitances between the gate electrodes and the semiconductor substrate. By this connection, a small size and a precise delay time of a delay circuit can be obtained.
Inventors
- 👤 Masayoshi Tomita
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 13:05
CPC Classifications
H; H03; H03H; H03H11/00; H03H11/02; H03H11/26; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/90; H10D84/903; H10D84/907
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
119 words
A method of constructing a delay circuit in a master slice IC, the method comprising the steps of: forming a plurality of metal-insulator semiconductor (MIS) transistors (Q n ,Qp) on a semiconductor substrate (20), each of the MIS transistors having a gate electrode formed over the semiconductor substrate through an insulating film; and selecting a wiring pattern (17-20) for connecting the MIS transistors to form various logic circuits; characterised by the further steps of: connecting one or more of the gate electrodes (62-65) of the MIS transistors to form a delay circuit (DLY) between two of the logic circuits, the delay circuit comprising resistance derived from the gate electrodes and capacitance between the gate electrodes and the semiconductor substrate.
Claim 2
Independent Claim
119 words
A method of constructing a delay circuit in a master slice IC, the method comprising the steps of: forming a plurality of metal-insulator semiconductor (MIS) transistors (Q n ,Qp) on a semiconductor substrate (20), each of the MIS transistors having a gate electrode formed over the semiconductor substrate through an insulating film; and selecting a wiring pattern (17-20) for connecting the MIS transistors to form various logic circuits; characterised by the further steps of: connecting one or more of the gate electrodes (62-65) of the MIS transistors to form a delay circuit (DLY) between two of the logic circuits, the delay circuit comprising resistance derived from the gate electrodes and capacitance between the gate electrodes and the semiconductor substrate.
Claim 3
Dependent Claim
68 words
A method as claimed in Claim 1, characterised in that the step of forming a plurality of MIS transistors comprises forming a plurality of P-channel MIS transistors (Q ) and N-channel MIS transistors (Q ), the P-channel MIS transistors and the N-channel MIS transistors being regularly arranged on the semiconductor substrate, the P-channel MIS transistors constituting P-channel gate arrays, and the N-channel MIS transistors constituting N-channel gate arrays.
Claim 4
Dependent Claim
52 words
A method as claimed in Claim 2, characterised in that the logic circuits comprise at least two CMIS inverters each constituted by one of the P-channel MIS transistors (Q ) and one of the N-channel MIS transistors (Q n ), and the delay circuit (DLY) is connected between the two CMIS inverters.
Claim 5
Dependent Claim
103 words
A method as claimed in Claim 3, characterised in that the step of connecting one or more of the gate electrodes (62-65) comprises connecting sequentially the output of an input logic circuit (INV 1 ) to one end of the first gate electrode (62) adjacent the input logic circuit, connecting the other end of the first gate electrode to one end of the second gate electrode (63) adjacent to the first gate electrode, and so on, and connecting the other end of the last gate electrode (65) adjacent an output logic circuit (INV 2 ) to the input of said output logic circuit.
Claim 6
Dependent Claim
29 words
A method as claimed in Claim 4, characterised in that the step of connecting gate electrodes is effected by aluminum wires ( L 6 - L 10 ) '
References Cited (Backward Citations)
No citation records indexed.
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