Test system for keyboard interface circuit

Claim 1

A test system for identifying an error condition between a keyboard interface and a processor comprising, in combination, a first shift register for storing, shifting and outputting coded data signals generated by said keyboard, a second shift register for storing, shifting and inputting coded data signals to be supplied to said keyboard, clock means for generating first and second timing signal sequences to facilitate operation of said first and second shift registers, means connecting the output of said second shift register to the input of said first shift register, said test system having an operating sequence comprising means for generating a test clock signal sequence and an inhibit signal sequence, clock switching means responsive to said inhibit signal sequence for inhibiting said first timing signal sequence being applied from said keyboard to said first and second shift registers and for applying said test clock signal sequence to said first and second shift registers, means responsive to said inhibit signal sequence for inhibiting coded data signals being applied from said keyboard to said first shift register, and comparison means for comparing said test clock signal sequence applied to said second shift register with the output signals from said first shift register to identify an error condition associated with said first and second shift registers.