US4435806A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Device for testing a circuit comprising sequential and combinatorial logic elements
Assignee: US Philips Corp
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Filing: 1981-07-13
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Granted: 1984-03-06
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Expires: 2001-07-13
Abstract
Abstract A device for processing digital signals includes combinatorial and sequential logic elements. For the testing of the device, a shift register can be formed from the sequential elements. A test pattern is applied thereto. The result of the processing of the test pattern is applied to the shift register. The output of the shift register is connected to a second shift register which forms a moving multibit sum pattern from a received series of result patterns by way of a feedback circuit to at least one Exclusive-OR-element. An output of the feedback circuit is connected to an input of the first shift register in order to apply a subsequent test pattern thereto. After completion of the test, the sum pattern formed is checked.
Inventors
- 👤 Marinus T. M. Segers
- 👤 Cornelis Niessen
- 👤 Krijn Kuiper
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 17:33
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/27
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
164 words
A digital signal processing device comprising a plurality of binary storage elements provided with control means to constitute a first shift register; said shift register having a first series input for receiving a test pattern, a first parallel output connected to signal processing elements in the device for presenting thereto said test pattern, a first parallel input connected to said signal processing elements for receiving therefrom a result pattern, and a first series output for outputting said result pattern; said digital signal processing device comprising a second shift register, said second shift register having a second serial output feeding said first serial input and feedback means; said feedback means comprising a retrocoupled connection for effecting an EXCLUSIVE-Or-function with at least one stage input of said second shift register; said second shift register having a verification output for feeding a verification means; and wherein said first and second shift registers have initializing means for receiving an initial signal pattern before the start of a test.
Claim 2
Dependent Claim
164 words
A digital signal processing device comprising a plurality of binary storage elements provided with control means to constitute a first shift register; said shift register having a first series input for receiving a test pattern, a first parallel output connected to signal processing elements in the device for presenting thereto said test pattern, a first parallel input connected to said signal processing elements for receiving therefrom a result pattern, and a first series output for outputting said result pattern; said digital signal processing device comprising a second shift register, said second shift register having a second serial output feeding said first serial input and feedback means; said feedback means comprising a retrocoupled connection for effecting an EXCLUSIVE-Or-function with at least one stage input of said second shift register; said second shift register having a verification output for feeding a verification means; and wherein said first and second shift registers have initializing means for receiving an initial signal pattern before the start of a test.
Claim 3
Dependent Claim
29 words
A device as claimed in claim 1, characterized in that the comparison element comprises an activation input (60) for receiving an activation signal at the end of a test.
Claim 4
Dependent Claim
34 words
A device as claimed in claim 1 or 2, characterized in that said feedback circuit consists of a single Exclusive-OR-gate which receives the serial output signal of the first and the second shift register.
Claim 5
Independent Claim
197 words
A method for testing a digital signal processing device comprising a plurality of binary storage elements and signal processing elements, said method comprising the steps of: a. providing an initial signal pattern for initializing all of said plurality of binary storage elements; b. presenting the contents of said plurality of binary storage elements in parallel to said signal processing elments for processing therein; c. presenting the results of said processing in said signal processing elements in parallel to said plurality of binary storage elements for storage therein, and forming an intermediate shift register from said binary storage elements; d. serially presenting the contents of said plurality of binary storage elements to a result shift register while retrocoupling at least one bit position output of said result shift register for exclusive OR-ing, at least one bit position input of said result shift register; e. serially presenting result output bits from said result shift register to said plurality of binary storage elements for constituting therein a further test signal pattern; f. repeating steps b, c, d, and e for a predetermined number of times; g. verifying the contents of said result shift register with a predetermined test result pattern.
Claim 6
Independent Claim
197 words
A method for testing a digital signal processing device comprising a plurality of binary storage elements and signal processing elements, said method comprising the steps of: a. providing an initial signal pattern for initializing all of said plurality of binary storage elements; b. presenting the contents of said plurality of binary storage elements in parallel to said signal processing elments for processing therein; c. presenting the results of said processing in said signal processing elements in parallel to said plurality of binary storage elements for storage therein, and forming an intermediate shift register from said binary storage elements; d. serially presenting the contents of said plurality of binary storage elements to a result shift register while retrocoupling at least one bit position output of said result shift register for exclusive OR-ing, at least one bit position input of said result shift register; e. serially presenting result output bits from said result shift register to said plurality of binary storage elements for constituting therein a further test signal pattern; f. repeating steps b, c, d, and e for a predetermined number of times; g. verifying the contents of said result shift register with a predetermined test result pattern.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-03-06 | 1987-09-05 | 1988-03-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-03-06 | 1991-09-05 | 1992-03-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-03-06 | 1995-09-05 | 1996-03-06 | $7700.00 | Window Closed / Lapsed |