US4285059A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for test of ultra high speed digital arithmetic units
Assignee: United States Department of the Army
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Filing: 1979-12-10
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Granted: 1981-08-18
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Expires: 1999-12-10
Abstract
Abstract A method is shown for testing ultra high speed digital arithmetic circuitsr even complete digital signal processors which operate at speeds faster than presently available test equipment. With this technique for testing, the operating speed of digital circuits can be increased until failures occur and then quantitative information on failure rates can be measured.
Inventors
- 👤 Donald W. Burlage
- 👤 James F. Lancaster
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 02:01
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2226; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
97 words
A method for testing ultra high speed digital equipment comprising the steps of selecting an input signal to be fed through the digital equipment; storing this input signal in a first shift register; selecting an expected output signal which should be presented if the input signal was fed through said digital equipment; storing this expected output signal in a second shift register; feeding the input signal from the first shift register into the digital equipment; and comparing the output from the digital equipment with the expected output signal stored in the second shift register to detect faults.
Claim 2
Independent Claim
97 words
A method for testing ultra high speed digital equipment comprising the steps of selecting an input signal to be fed through the digital equipment; storing this input signal in a first shift register; selecting an expected output signal which should be presented if the input signal was fed through said digital equipment; storing this expected output signal in a second shift register; feeding the input signal from the first shift register into the digital equipment; and comparing the output from the digital equipment with the expected output signal stored in the second shift register to detect faults.
Claim 3
Dependent Claim
93 words
A method as set forth in claim 1 further comprising the steps of recirculating the input signal out of the first shift register back into the input of the first shift register so as to provide consecutive insertions of the input signal into the digital equipment; and recirculating the output of the expected output signal of the second shift register back into the input of the second shift register so as to provide consecutive outputs of the expected output signal so that they can be compared with the outputs of the digital equipment.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-08-17 | 1985-02-16 | 1985-08-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-08-17 | 1989-02-16 | 1989-08-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-08-17 | 1993-02-16 | 1993-08-18 | $7700.00 | Window Closed / Lapsed |