CMOS high voltage switch

Claim 1

A CMOS high voltage for interfacing between a decoder output and an input to an erasable, programmable read-only-memory comprising: input means for receiving an input signal from the output of one decoder; said input means being formed of an inverter consisting of a P-channel MOS transistor and an N-channel MOS transistor whose gate electrodes are connected together to define its input and whose drain electrodes are connected together to define its output the source of said P-channel transistor being connected to a first lower supply potential, the source of the N-channel transistor being connected to a ground potential; a control device having conduction path and a gate electrode, one end of the conduction path being connected to the output of said input means, the other end of the conduction path being connected to an output node, the gate electrode being connected to the first lower supply potential: said control device being former of an N-channel MOS pass transistor having its drain connected to the output of said inverter and its source connected to the output node: pump means connected to said other end of conduction gate for pumping the output node to a first higher voltage outing a first mode of operation: said pump means including an N-channel MOS current-limiting transistor having its drain connected to a second higher supply potential, its gate connected to the source of said base transistor, its source connected to the gate and drain electrodes of a first N-channel MOS charge transfer transistor serving as a diode and to one end of a capacitor, the source of said first charge transfer transistor being connected to the source of said pass transistor, the other end of the capacitor being connected to a free-running oscillator: switching means connected also to said other end of the conduction path for switching the output node to a second lower voltage during second mode of operation: and said switching means including a P-channel MOS switching transistor and a first P-channel MOS current-limiting transistor, said switching transistor having its source connected to the first lower supply potential, its gate connected to a logic voltage and its drain connected to source of said first P-channel current-limiting transistor, said first P-channel current-limiting transistor having its gate connected to the output of said decoder and it drain connected to the output node.