Programmable digital hysteresis circuit

Claim 2

Digital control apparatus for stabilizing the value of an input digital signal having error components superposed thereon by interposing a predetermined value of hysteresis, comprising: data output means for generating a reference digital signal for energizing a digital display, digital data store means for storing correction factor signals in binary form representative of differences between said input digital signal and said reference digital signal for differences that exceed said predetermined value of hysteresis and for storing a quiescent command representative of no change in said reference digital signal for differences that do not exceed said predetermined value of hysteresis, means to apply said input digital signal and said reference digital signal to said digital data store means, means for reading out said correction factor signals from said digital data store means corresponding to said applied signals, and means for applying said correction factor signals to said data output means so as to increment or decrement said output means in a direction to reduce differences between said input digital signal and said reference digital signal when said differences exceed said predetermined value of hysteresis and for applying said quiescent command to said data output means so as to effect no change in said reference digital signal when said differences do not exceed said predetermined value of hysteresis.

Claim 3

Apparatus as set forth in claim 1, said data output means further comprising up/down counting means for incrementing and decrementing said reference digital signal in accordance with said correction factor signals, thereby reducing said difference to within said predetermined value of hysteresis.

Claim 4

Apparatus as set forth in claim 2, further comprising logic means responsive to said correction factor signals and to a source of clock pulses for periodically sampling and correcting said counter means in accordance therewith.

Claim 5

Apparatus as set forth in claim 3, wherein said logic means includes NAND gate means.

Claim 6

Apparatus as set forth in claim 1, wherein said digital data store means includes addressable memory means comprising a predetermined array of binary digital words corresponding to predetermined values of said differences.

Claim 7

Apparatus as set forth in claim 5, wherein said memory means includes a programmable read only memory.

Claim 8

Apparatus as set forth in claim 6, wherein said digital data store means comprises a plurality of storage locations corresponding respectively to a plurality of differences between said input digital signal and said reference digital signal, and each storage location contains a binary word defining a difference value corresponding to a correction factor to be applied to said data output means.

Claim 9

Apparatus as set forth in claim 7, wherein said digital data store means comprises; means for receiving parallel input groups of binary digital signals, means for providing parallel output groups of binary digital signals corresponding to said input groups, said input digital signal and said reference digital signal each comprising high order and low order groups of said parallel input signals, said means to apply said input digital signal and said reference digital signal to said digital data store means including means for combining a high order group of said reference digital signal and a high order group of said binary digital signal, means for applying said combined high order groups of reference digital signal and binary digital signal to a first digital data store means, said means to apply said input digital signal and said reference digital signal further including means for combining a low order group of said reference digital signal and a low order group of said binary digital signal, means for applying said combined low order groups of reference digital signal and binary digital signal to a second digital store means. said first and second digital data store means respectively adapted to provide a further high order and low order groups of binary digital signals to a third digital data store means, said third digital data store means providing command signals responsive to said differences to said up/down counting means.

Claim 10

Apparatus as set forth in claim 8, wherein said digital data store means comprises at least three components, including locations representing an increment command, a decrement command, and said quiescent command.

Claim 11

Apparatus as set forth in claim 9, further comprising a fourth component having a location representing a boundary condition which is indeterminate of a command condition.