US4499547A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Output compensating system
Assignee: Fujinon Corp
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Filing: 1981-08-13
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Granted: 1985-02-12
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Expires: 2001-08-13
Abstract
Abstract A system for compensating for variations in an output consisting of many components that show variations, comprising a memory for storing the compensation value for each component, an analog-to-digital converter for converting the output into several bits of digital output, a multiplier for multiplying the value of the high order bits of the digital output by the compensation value, and a subtracter for subtracting the output of the multiplier from the value of the low order bits. Instead of using the multiplier, the order of the value of the high order bits can be lowered down to that of the value of the low order bits, and the obtained value can be subtracted from the low order bits the number of times indicated by the compensation value.
Inventors
- 👤 Masafumi Inuiya
- 👤 Makoto Murakoshi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:18
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/40; H04N1/401
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
134 words
A system for compensating for variation in an output for each of a plurality of components in which said output has relatively small variations proportional to the magnitude of inputs, comprising a memory means for storing a compensation value (B) predetermined for each component with reference to a given unit level of output on the basis of the variation among said components, an analog-to-digital conversion means for converting said output into several bits of digital output, a multiplication means for multiplying the value (A) of the high order bits of said digital output by the compensation value (B) stored in said memory means, and a subtraction means for subtracting the output (A×B) of said multiplication means from the value (C) of the low order bits of said digital output and outputting a compensating signal.
Claim 2
Independent Claim
134 words
A system for compensating for variation in an output for each of a plurality of components in which said output has relatively small variations proportional to the magnitude of inputs, comprising a memory means for storing a compensation value (B) predetermined for each component with reference to a given unit level of output on the basis of the variation among said components, an analog-to-digital conversion means for converting said output into several bits of digital output, a multiplication means for multiplying the value (A) of the high order bits of said digital output by the compensation value (B) stored in said memory means, and a subtraction means for subtracting the output (A×B) of said multiplication means from the value (C) of the low order bits of said digital output and outputting a compensating signal.
Claim 3
Independent Claim
152 words
A system for compensating for variation in an output for each of a plurality of components in which the said output has relatively small variations proportional to the magnitude of inputs, comprising a memory means for storing a compensation value (B) predetermined for each component with reference to a given unit level of output on the basis of the variation among said components, an analog-to-digital conversion means for converting said output into several bits of digital output, means for lowering the order of the value (A) of the high order bits of said digital output to coincide with the order of the value (C) of the lower order bits of said digital output, a subtraction means which subtracts the value (A) of high order bits a number of times, as determined by said compensation value B, from the value (C) of the low order bits, and means for outputting a compensated signal.
Claim 4
Independent Claim
152 words
A system for compensating for variation in an output for each of a plurality of components in which the said output has relatively small variations proportional to the magnitude of inputs, comprising a memory means for storing a compensation value (B) predetermined for each component with reference to a given unit level of output on the basis of the variation among said components, an analog-to-digital conversion means for converting said output into several bits of digital output, means for lowering the order of the value (A) of the high order bits of said digital output to coincide with the order of the value (C) of the lower order bits of said digital output, a subtraction means which subtracts the value (A) of high order bits a number of times, as determined by said compensation value B, from the value (C) of the low order bits, and means for outputting a compensated signal.
References Cited (Backward Citations)
US3828175A
Cited
US3949162A
Cited
US4323977A
Cited
US4303984A
Cited
US4317134A
Cited
US4298887A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-02-12 | 1988-08-13 | 1989-02-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-02-12 | 1992-08-13 | 1993-02-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-02-12 | 1996-08-13 | 1997-02-12 | $7700.00 | Window Closed / Lapsed |