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US4686455A
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Method for the localization of time-critical events within a clock electronic circuit
Assignee: Siemens AG
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Filing: 1984-08-02
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Granted: 1987-08-11
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Expires: 2004-08-02
Abstract
Abstract Time-critical events are localized within a clocked electronic circuit without requiring cyclical operation By way of measuring at the outputs of the circuit, the limit frequency of the circuit is identified. A test pattern sequence is then applied to this circuit. The number n of that test pattern at which errors are perceived at the outputs is identified, in particular with a clock frequency higher than the identified limit frequency of the circuit. The test patterns having the numbers n-m are applied to the circuit with a clock frequency greater than the identified limit frequency of the circuit and the remaining n test patterns are applied to the circuit with a clock frequency lower than the identified limit frequency of the circuit, being applied thereto in succession step-by-step with m=1,2,3 . . . in at least one run of n test patterns. A check is carried out after every run of a test pattern sequence of n test patterns as to whether an error still exist at the output until an error can no longer be documented at the output and a determination is thus made with respect to which test pattern having the number n-m the error is generated within the -circuit. An error tracking technique is carried out in order to localize the cause of error within the electronic circuit.
Inventors
- 👤 Reiner Lassmann
- 👤 Albert Krupp
- 👤 Peter Fazekas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 15:07
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/302; G01R31/305
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
364 words
A method for localizing time-critical events within a clocked electronic circuit which comprises a plurality of interconnected logic elements and which has a limit frequency at which the circuit cannot function properly, comprising the steps of: applying increasing clock frequencies to the electronic circuit and measuring the outputs of the circuit to identify the limit frequency of the circuit; applying a sequence of test patterns to the circuit at a clock frequency which is greater than the identified limit frequency and with the test pattern sequence composed of individual test patterns which are applied in a defined succession and measuring the outputs of the circuit for an error perceived at a number n of an individual test pattern at which the error is perceived, where n is defined by the position of the individual error-causing test pattern in the test pattern sequence; applying to the circuit the individual test patterns preceding the test pattern n in the test pattern sequence and the test pattern n in the sequence corresponding to the original test pattern sequence by applying the first n-m test patterns to the circuit with a clock frequency which is greater than the limit frequency and by applying the m test patterns following the test pattern n-m with a clock frequency which is lower than the limit frequency, where m=1 and is respectively increased by one unit after each run of the n test patterns and measuring the output after each run of the n test patterns to determine whether the error is still present at the output of the circuit; and repeating the steps of applying the test patterns preceding the test pattern n in the test pattern sequence and the test pattern n with the first n-m test patterns applied at the clock frequency greater than the limit frequency and the m test patterns following the test pattern n-m until an error no longer appears at the output of the circuit and, therefore, an identification is made that the test pattern n-M generates the error within the circuit, where M is the number of runs of the n test patterns; and performing error tracking to localize the cause of the error.
Claim 2
Independent Claim
364 words
A method for localizing time-critical events within a clocked electronic circuit which comprises a plurality of interconnected logic elements and which has a limit frequency at which the circuit cannot function properly, comprising the steps of: applying increasing clock frequencies to the electronic circuit and measuring the outputs of the circuit to identify the limit frequency of the circuit; applying a sequence of test patterns to the circuit at a clock frequency which is greater than the identified limit frequency and with the test pattern sequence composed of individual test patterns which are applied in a defined succession and measuring the outputs of the circuit for an error perceived at a number n of an individual test pattern at which the error is perceived, where n is defined by the position of the individual error-causing test pattern in the test pattern sequence; applying to the circuit the individual test patterns preceding the test pattern n in the test pattern sequence and the test pattern n in the sequence corresponding to the original test pattern sequence by applying the first n-m test patterns to the circuit with a clock frequency which is greater than the limit frequency and by applying the m test patterns following the test pattern n-m with a clock frequency which is lower than the limit frequency, where m=1 and is respectively increased by one unit after each run of the n test patterns and measuring the output after each run of the n test patterns to determine whether the error is still present at the output of the circuit; and repeating the steps of applying the test patterns preceding the test pattern n in the test pattern sequence and the test pattern n with the first n-m test patterns applied at the clock frequency greater than the limit frequency and the m test patterns following the test pattern n-m until an error no longer appears at the output of the circuit and, therefore, an identification is made that the test pattern n-M generates the error within the circuit, where M is the number of runs of the n test patterns; and performing error tracking to localize the cause of the error.
Claim 3
Dependent Claim
153 words
The method of claim 1, wherein the step of performing error tracking is defined as: applying the first n-M test patterns to the circuit at a frequency greater than the limit frequency in a plurality of runs of the n test patterns; in each run, applying the M-p test patterns following the test patterns n-M, where p=1,2 . . . , and at a frequency lower than the limit frequency of the circuit; after each test pattern run in which p is respectively incremented in steps by one unit, checking the logical states at the output of a circuit element recognized as faulty in the preceding test pattern run as to whether a faulty logical state of the input to this circuit element is present; and identifying at least one circuit element as causing an error by detecting a faulty logical state at the output with no faulty logical state at the input.
Claim 4
Dependent Claim
44 words
The method of claim 1, wherein the step of error path tracking is further defined as: backtracking in m sequential stages proceeding from a faulty output of the circuit and checking the outputs and inputs of each logic element which could cause the error.
Claim 5
Dependent Claim
29 words
The method of claim 3, wherein the step of checking is further defined as: checking only those logic elements whereat the test pattern n-M causes generation of the error.
Claim 6
Dependent Claim
23 words
The method of claim 4, and further comprising the step of: applying additional test patterns to check the connections between the logic elements.
Claim 7
Dependent Claim
32 words
The method of claim 5, and further comprising the step of: measuring signal values arising in response to the test patterns at internal circuit nodes by applying a probe to each node.
Claim 8
Dependent Claim
23 words
The method of claim 6, wherein the step of applying a probe is further defined as: applying an electron probe to each node.
Claim 9
Dependent Claim
23 words
The method of claim 6, wherein the step of measuring signal values is further defined as: applying a laser scanner to each node.
Claim 10
Dependent Claim
25 words
The method of claim 6, wherein: the step of measuring signals is performed after two clock pulses and before the conclusion of a test run.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-08-10 | 1991-02-09 | 1991-08-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-08-10 | 1995-02-09 | 1995-08-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-08-10 | 1999-02-09 | 1999-08-11 | $7700.00 | Window Closed / Lapsed |