US4685106A
Expired / Lapsed
US
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High rate multiplexer
Assignee: Unisys Corp
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Filing: 1984-08-31
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Granted: 1987-08-04
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Expires: 2004-08-31
Abstract
Abstract A high rate multiplexing system which is capable of operating on multiple channels while ensuring synchronization of the system operation. The system includes a basic timing network for synchronizing the system operation. Automatic phase adjusters are used to re-align data signals with a clock signal whenever data transitions occur while the data is being sampled. Synchronizing circuits are used to insert synchronization data bits into the multiplexed data streams where appropriate. A medium rate multiplexer generates two different data streams, certain clock signals and strobe signals. A higher rate multiplexer is capable of operation in different modes, including but not limited to wideband operation or narrow band operation. A Manchester encoder combines data output signals into a single aggregate data stream.
Inventors
- 👤 Larry J. Miller
- 👤 Glen D. Rattlingourd
- 👤 Clifford T. Johnson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 17:34
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/16; H04J3/1605; H04J3/1623; H04J3/1647
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
185 words
A multiplexing system comprising, timer means for producing a plurality of timing signals, said timer means adapted to receive a master clock signal and produce a plurality of timing signals including reduced rate clock signals which are supplied to other circuit components in said system, phase adjuster means for aligning input data signals with internal timing signals from said timer means, first multiplexer means capable of operation at a first rate connected to receive signals from said timer means and from said phase adjuster means and to supply output signals which are representative of the input data signals and the internal timing signals, said first multiplexer means includes first synchronizer means which synchronizes the operation of said first multiplexer means, and second multiplexer means capable of operation at a second rate other than said first rate connected to receive signals from said timer means and from said phase adjuster means and to produce output signals which are representative of the input data signal and the internal timing signals, said second multiplexer means includes second synchronizer means which synchronizes the operation of said second multiplexer means.
Claim 2
Dependent Claim
185 words
A multiplexing system comprising, timer means for producing a plurality of timing signals, said timer means adapted to receive a master clock signal and produce a plurality of timing signals including reduced rate clock signals which are supplied to other circuit components in said system, phase adjuster means for aligning input data signals with internal timing signals from said timer means, first multiplexer means capable of operation at a first rate connected to receive signals from said timer means and from said phase adjuster means and to supply output signals which are representative of the input data signals and the internal timing signals, said first multiplexer means includes first synchronizer means which synchronizes the operation of said first multiplexer means, and second multiplexer means capable of operation at a second rate other than said first rate connected to receive signals from said timer means and from said phase adjuster means and to produce output signals which are representative of the input data signal and the internal timing signals, said second multiplexer means includes second synchronizer means which synchronizes the operation of said second multiplexer means.
Claim 3
Dependent Claim
33 words
The system recited in claim 1 wherein, said phase adjuster means includes high speed phase adjusters connected to said second multiplexer means and lower speed phase adjusters connected to said first multiplexer means.
Claim 4
Dependent Claim
25 words
The system recited in claim 1 including pseudo-number generator means which supplies a pseudo-numder code to said first multiplexer means via said phase adjuster means.
Claim 5
Dependent Claim
30 words
The system recited in claim 3 wherein, said pseudo-number generator means receives a clock signal and supplies a pseudo-number signal to said first multiplexer means via said phase adjuster means.
Claim 6
Dependent Claim
32 words
The system recited in claim 1 including, code generator means connected to said second multiplexer means to selectively overlay a code signal on the data streams supplied to said second multiplexer means.
Claim 7
Dependent Claim
28 words
The system recited in claim 5 wherein, said code generator means receives clock signals from said timer means and supplies a pseudo-number signal to said second multiplexer means.
Claim 8
Dependent Claim
39 words
The system recited in claim 5 wherein, said first synchronizer means is connected to said pseudo-number generator means to control the operation of said pseudo-number generator means and the application of a pseudo-number signal to said first multiplexer means.
Claim 9
Dependent Claim
18 words
The system recited in claim 1 including, encoding means connected to receive signals from said second multiplex means.
Claim 10
Dependent Claim
19 words
The system recited in claim 8 wherein, said encoding means is connected to provide a Manchester encoded output signal.
Claim 11
Dependent Claim
17 words
The system recited in claim 9 wherein, said encoding means produces a Miller frequency modulation output signal.
Claim 12
Dependent Claim
38 words
The system recited in claim 1 wherein, said phase adjuster means includes a plurality of phase adjusting circuits which assure a proper relationship between the input data signals and the respective timing signals produced by said timer means.
Claim 13
Dependent Claim
23 words
The system recited in claim 1 wherein, said second multiplexer means is capable of narrowband and wideband operation which have different frequency rates.
Claim 14
Dependent Claim
26 words
The system recited in claim 1 wherein, said second synchronizer means generates sync bits which are inserted into the signal streams in said second multiplexer means.
Claim 15
Dependent Claim
20 words
The system recited in claim 13 wherein, each of said first and second synchronizing means generates a Barker code signal.
Claim 16
Dependent Claim
20 words
The system recited in claim 14 wherein, said second synchronizing means also generates the complement of said Barker code signal.
Claim 17
Dependent Claim
26 words
The system recited in claim 1 wherein, said first synchronizer means generates sync bits which are inserted into the signal streams in said first multiplexer means.
Claim 18
Dependent Claim
20 words
The system recited in claim 1 wherein, said phase adjuster means receive said input data signals from external user devices.
Claim 19
Dependent Claim
24 words
The system recited in claim 17 wherein, said phase adjuster means prevent the sampling of said input data signals at a transition portion thereof.
Claim 20
Dependent Claim
25 words
The system recited in claim 1 wherein, said second multiplexer means is arranged to operate on at least two different streams of input data signals.
Claim 21
Dependent Claim
22 words
The system recited in claim 19 wherein, said second multiplexer means produces two output data streams at quadrature and the complements thereof.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-08-03 | 1991-02-02 | 1991-08-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-08-03 | 1995-02-02 | 1995-08-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-08-03 | 1999-02-02 | 1999-08-04 | $7700.00 | Window Closed / Lapsed |