US3924079A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Latching multiplexer circuit
Assignee: Motorola Solutions Inc
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Filing: 1974-01-02
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Granted: 1975-12-02
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Expires: 1994-01-02
Abstract
Abstract An eight by eight multiplex system is disclosed which is capable of independently switching any one of eight inputs to any one of eight outputs at will. This is accomplished through eight multiplex decoding gate matrices under the control of an address memory individually associated with each matrix to couple the output of that matrix with the desired one of the input leads. The address memories may be continuously synchronously updated with address information; they may be set once when the system is initially put into operation; or they may be changed at any random intervals depending upon the use to which the multiplex system is placed. Disclosure is made of both linear and digital versions, and the linear version is capable of two-way interchange of information between the input and output terminals.
Inventors
- 👤 Lane S Garrett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 23:28
CPC Classifications
H; H04; H04L; H04L5/00; H04L5/22; H04L5/24; H04L5/245; H04J; H04J3/00; H04J3/02; H04J3/04; H04J3/047
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
223 words
A system for selectively transferring data appearing on any one of N input terminals to any one of M output terminals, where N and M are positive integers, including in combination: M decoding gate means each having an output coupled to one of said M output terminals and having N inputs coupled to said N input terminals, respectively; M address memory means, each comprising a binary register having a predetermined number of output terminals capable of producing at least N different binary number output combinations, the output terminals of each of said address memory means coupled to a different one of said M decoding gate means for causing such decoding gate to interconnect a predetermined one of said N inputs thereof with the output thereof in accordance with the binary number appearing on the output terminals of said address memory means; means for supplying a binary address input in common to all of said M address memory means; ring counter circuit means having at least M output terminals each coupled with a different respective one of said M address memory means for enabling said address memory means sequentially to store in said binary register of each of said address memory means the binary address input supplied thereto only when said binary registers are enabled by an output from said ring counter circuit means.
Claim 2
Independent Claim
223 words
A system for selectively transferring data appearing on any one of N input terminals to any one of M output terminals, where N and M are positive integers, including in combination: M decoding gate means each having an output coupled to one of said M output terminals and having N inputs coupled to said N input terminals, respectively; M address memory means, each comprising a binary register having a predetermined number of output terminals capable of producing at least N different binary number output combinations, the output terminals of each of said address memory means coupled to a different one of said M decoding gate means for causing such decoding gate to interconnect a predetermined one of said N inputs thereof with the output thereof in accordance with the binary number appearing on the output terminals of said address memory means; means for supplying a binary address input in common to all of said M address memory means; ring counter circuit means having at least M output terminals each coupled with a different respective one of said M address memory means for enabling said address memory means sequentially to store in said binary register of each of said address memory means the binary address input supplied thereto only when said binary registers are enabled by an output from said ring counter circuit means.
Claim 3
Dependent Claim
34 words
The combination according to claim 1 wherein each of said decoding gate means passes information from the interconnected one of said inputs to said output thereof and from said output to said interconnected input.
Claim 4
Dependent Claim
53 words
The combination according to claim 1 wherein each of said binary registers comprises a plurality of binary latching switches having first and second stable states of operation and settable by an enabling signal from said ring counter means coinciding with binary address inputs representative of either of said first or second stable states.
Claim 5
Dependent Claim
107 words
The combination according to claim 3 wherein each of said decoding gate means comprises M digital logic gate circuits each coupled with a different one of said N inputs and each enabled by a different one the N binary number output combinations from said binary register coupled thereto so that only one of said digital logic gate circuits is enabled to pass signals from the data input with which it is connected to its output; and OR gate means coupled to the outputs of all of said digital logic gate circuits, with the outpuT of said OR gate means comprising the output of said decoding gate means.
Claim 6
Dependent Claim
30 words
The combination according to claim 1 further including M transmission gates, each coupling the output of a corresponding decoding gate means with a different one of said M output terminals.
Claim 7
Dependent Claim
18 words
The combination according to claim 5 further including means for controlling the conductivity of said transmission gate means.
Claim 8
Dependent Claim
50 words
The combination in accordance to claim 1 wherein each of said address memory means comprises at least one bistable latching circuit settable to one or the other of two stable states in accordance with the simultaneous occurrence of a corresponding address input signal and enabling signal from said counter means.
Claim 9
Dependent Claim
38 words
The combination according to claim 7 wherein each of said address memory means, includes a plurality of bistable latching circuits arranged to represent binary weighted digits, with the outputs thereof representing at least N different stored address inputs.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-12-01 | 1979-06-02 | 1979-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-12-01 | 1983-06-02 | 1983-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-12-01 | 1987-06-02 | 1987-12-02 | $7700.00 | Window Closed / Lapsed |