Clock gated digital data encoding circuit

Claim 2

A digital data encoding circuit connected to a multibit source of input digital data signals including: multiplexer means comprising a plurality of addressable input terminals connected to said data source, an output terminal, and a plurality of address terminals; said multiplexer means being responsive to address signals applied to said address terminals for applying to said output terminal the input digital data signal applied to the input terminal corresponding to the applied address signals; clock means providing a fixed frequency clock signal; multi-stage counter means connected to said clock means, with the first stage of said counter means providing an output signal at half the frequency of said clock signal, and each succeeding stage of said counter means providing an output signal at half the frequency of the preceding stage; address means connected between said multiplexer means address terminals and the third and higher stages of said counter means for applying said address signals to sequentially address the input terminals of said multiplexer means; and encoder means having input terminals connected to said multiplexer means output terminal and the first and second stages of said counter means for encoding each bit of said data source into a four-chip binary code and applying the binary coded data to an output terminal of said encoder means.

Claim 3

The circuit of claim 1, wherein said encoder means includes: means responsive to the first and second stage counter means output signals for generating four time slot signals; means responsive to the first time slot signal for applying to said encoder means output terminal a signal at a first binary level; means responsive to the fourth time slot signal for applying to said encoder means output terminal a signal at the second binary level; and means responsive to the second and third time slot signals for applying to said encoder means output terminal a signal corresponding to the level of said each data bit.

Claim 4

In a one-way digital data transmission system wherein a plurality of switches selectively provide binary input data and a transmitter means is selectively enabled to transmit a multibit message including said data, apparatus for generating said message and enabling said transmitter including: clock means providing a fixed frequency clock signal; counter means connected to receive said clock signal; said counter means comprising a plurality of serially connected frequency divider stages, the first of said stages providing a signal at half the frequency of said clock signal and each of the succeeding stages providing a respective signal at half the frequency of the preceding stage; multiplexer means having a plurality of addressable input terminals connected to said switches, an output terminal, and a plurality of address terminals connected to receive the signals provided by the third and higher stages of said counter means; said multiplexer means applying a multibit message to said output terminal by sequentially coupling to said output terminal the input terminals identified by the signals provided by said third and higher counter means stages; encoder means connected to said multiplexer means output terminl and the first and second stages of said counter means for encoding each bit of the message on said multiplexer output terminal into a four-chip binary code wherein the first chip has a first binary value and the fourth chip has the other binary value, said encoder means providing the encoded message bits to said transmitter means; and enabling means connected to said counter means and said transmitter means for repetitively enabling said transmitter means for a first interval of time long enough to transmit said multibit message during a substantially longer second interval of time.

Claim 5

In a one-way digital data transmission system wherein a plurality of switches selectively provide binary input data and a transmitter means is selectively enabled to transmit a multibit message including said data, apparatus for generating said message and enabling said transmitter including: clock means providing a fixed frequency clock signal; counter means connected to receive said clock signal; said counter means comprising a plurality of serially connected frequency divider stages, the first of said stages providing a signal at half the frequency of said clock signal and each of the succeeding stages providing a respective signal at half the frequency of the preceding stage; multiplexer means having a plurality of addressable input terminals connected to said switches, an output terminal, and a plurality of address terminals connected to receive the signals provided by the third and higher stages of said counter means; said multiplexer means applying a multibit message to said output terminal by sequentially coupling to said output terminal the input terminals identified by the signals provided by said third and higher counter means stages; encoder means connected to said multiplexer means output terminl and the first and second stages of said counter means for encoding each bit of the message on said multiplexer output terminal into a four-chip binary code wherein the first chip has a first binary value and the fourth chip has the other binary value, said encoder means providing the encoded message bits to said transmitter means; and enabling means connected to said counter means and said transmitter means for repetitively enabling said transmitter means for a first interval of time long enough to transmit said multibit message during a substantially longer second interval of time.

Claim 6

The apparatus of claim 3, wherein said plurality of switches comprises a first group of switches and a second group of switches, and further including: sensing means responsive to the closing of a switch in said first group for providing a priority signal; and means responsive to said priority signal for controlling said enabling means to shorten said second interval of time.

Claim 7

The apparatus of claim 3, wherein said encoder means includes: means responsive to the first and second stage counter means output signals for generating four time slot signals; means responsive to the first time slot signal for providing to said transmitter means a signal at a first binary level; means responsive to the fourth time slot signal for providing to said transmitter means a signal at the second binary level; and means responsive to the second and third time slot signals for providing to said transmitter means a signal corresponding to the level of said each message bit.

Claim 8

The apparatus of claim 3, wherein said enabling means includes manually operable means for resetting said counter means and enabling said transmitter means.

Claim 9

The apparatus of claim 3, wherein said multiplexer means includes, three eight-input multiplexer units having their respective output terminals connected to said multiplexer means output terminal, each of said multiplexer units including three address terminals and an inhibit terminal, a first level signal on an inhibit terminal causing a fixed level signal to appear on the respective output terminal and a second level signal on the inhibit terminal allowing the signals on the respective input terminals to appear on the output terminal in accordance with the applied address signals, the corresponding address terminals of said multiplexer units being connected to the third, fourth, and fifth stages of said counter means, and the inhibit terminals of said multiplexer units being connected to the sixth, seventh, and eighth stages of said counter means to generate a 64-bit message from the inputs to said three multiplexer units.