Control circuit for a centrex attendant console interface

Claim 1

A control circuit for effecting the transfer of data messages between an interface circuit and a CENTREX equipped central office exchange, said central office exchange including an analog control unit connected to a peripheral processor, said analog control unit including a control field for sending control signals to said control circuit and said interface circuit including an input sequential memory for receiving data messages from said peripheral processor, said control circuit comprising: gating means including first and second inputs connected to said control field arranged to produce a logic high output signal responsive to the simultaneous application of a first and a second control signal; first bistable memory means having a data input, a reset input and at least one output, said gating means output signal connected to said data input and said bistable memory means further including a clock input connected to a write select signal from said peripheral processor and in response to said write select signal said gating means output signal is stored in said first bistable memory means and applied to said output; second bistable memory means having a data input and first and second outputs, said first bistable memory means output is connected to said second bistable memory means data input, and said second bistable memory means further including a clock input connected to a source of clocking signals where during a first rising edge of said clocking signal said second bistable memory means inputs said output signal from said first bistable memory means and outputs a logic high output signal from said first output and a logic low signal from said second output; and second gating means having first and second inputs and an output connected to said input sequential memory means, said first input connected to said second bistable memory means first output and said second input connected to said control field whereby, in response to the simultaneous presence of an input sequential memory enabling signal on said second input and the logic high output by said second bistable memory means a shift-in signal is generated and applied to said input sequential memory allowing said memory to receive data messages from said peripheral processor.