US4685053A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable controller with fault detection
Assignee: Fanuc Corp
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Filing: 1984-12-05
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Granted: 1987-08-04
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Expires: 2004-12-05
Abstract
Abstract An input signal (A) and an output signal (B) with respect to an output memory (8), and an output signal (C) of an output circuit (9) in a programmable controller are compared with each other. The identification of and an abnormal part is displayed in accordance with the comparison results.
Inventors
- 👤 Kiyoshi Hattori
- 👤 Eiji Usuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:02
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/05; G05B19/058; G05B2219/00; G05B2219/10; G05B2219/11; G05B2219/1181; G05B2219/1185; G05B2219/14; G05B2219/14039
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
247 words
A programmable controller connectable to an external unit, comprising: a central processing unit for providing a first signal; an output memory, coupled to said central processing unit, for storing the first signal from said central processing unit and for providing, as an output, a second signal, the second signal also being fed back to said central processing unit; an output circuit, coupled to said central processing unit and said output memory, and connectable to the external unit, for receiving the second signal from said output memory and for providing, as an output to the external unit, a third signal, said output circuit including means for feeding back the third signal to said central processing unit, said output circuit and said output memory being susceptible to damage and abnormal operation when said output circuit is connected to the external unit, said central processing unit including: means for comparing the first and third signals, for comparing the first and second signals and for generating a first abnormality signal indicative of an abnormality in said output circuit if the first and third signals do not coincide and for generating a second abnormality signal indicative of an abnormality in said output memory if the first and second signals do not coincide; and a display device, coupled to said central processing unit, for providing a display identifying an abnormality in one of said output circuit and said output memory when the corresponding one of the first and second abnormality signals is generated.
Claim 2
Dependent Claim
247 words
A programmable controller connectable to an external unit, comprising: a central processing unit for providing a first signal; an output memory, coupled to said central processing unit, for storing the first signal from said central processing unit and for providing, as an output, a second signal, the second signal also being fed back to said central processing unit; an output circuit, coupled to said central processing unit and said output memory, and connectable to the external unit, for receiving the second signal from said output memory and for providing, as an output to the external unit, a third signal, said output circuit including means for feeding back the third signal to said central processing unit, said output circuit and said output memory being susceptible to damage and abnormal operation when said output circuit is connected to the external unit, said central processing unit including: means for comparing the first and third signals, for comparing the first and second signals and for generating a first abnormality signal indicative of an abnormality in said output circuit if the first and third signals do not coincide and for generating a second abnormality signal indicative of an abnormality in said output memory if the first and second signals do not coincide; and a display device, coupled to said central processing unit, for providing a display identifying an abnormality in one of said output circuit and said output memory when the corresponding one of the first and second abnormality signals is generated.
Claim 3
Dependent Claim
56 words
A programmable controller according to claim 1, wherein said feedback means of said output circuit comprises: a first buffer, connected to said output memory, for receiving the second signal; a transistor connected to said first buffer; a diode connected to said transistor; and a second buffer connected to said diode and to said central processing unit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-08-03 | 1991-02-02 | 1991-08-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-08-03 | 1995-02-02 | 1995-08-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-08-03 | 1999-02-02 | 1999-08-04 | $7700.00 | Window Closed / Lapsed |