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US4682328A
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Dynamic memory refresh and parity checking circuit
Assignee: Microsemi Semiconductor ULC
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Filing: 1985-09-27
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Granted: 1987-07-21
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Expires: 2005-09-27
Abstract
Abstract A circuit for use in conjunction with a microprocessor for refreshing, checking and correcting data signals stored in a dynamic memory. The circuit utilizes a direct memory access controller for transferring data signals stored in successive locations of the dynamic memory to a non-existent peripheral. Data signals appearing on a data bus as a result of the data transfer, are applied to a parity checking circuit for generating an interrupt signal to the microprocessor in response to detection of parity errors in the data signal. The microprocessor then performs a data recovery routine in which correct versions of the data signal stored in a non-volatile memory, are transferred for storage in the dynamic memory under control of a microprocessor. Parity errors in data signals stored in the dynamic memory are thus corrected prior to being accessed by the microprocessor.
Inventors
- 👤 John R. Ramsay
- 👤 Zbigniew B. Styrna
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 21:58
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1048; G06F11/106; G06F11/14; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F13/282; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096; G11C7/00; G11C7/10; G11C7/1006
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
211 words
A circuit for refreshing, checking and correcting data signals stored in a dynamic memory, comprising: (a) a data bus for connection to said dynamic memory, (b) a direct memory access controller for connection to said memory and said data bus, for periodically reading successive ones of said data signals such that said data signals appear on said data bus, (c) a parity checking circuit, connected to said data bus, for detecting parity errors in said data signals and generating interrupt signals in response thereto, (d) recovery means connected to said data bus and said parity checking circuit, for receiving said interrupt signals and generating and storing correct versions of said data signals in said dynamic memory in response thereto, and (e) said recovery means being comprised of non-volatile memory means containing said correct versions of said data signals and means for retrieving said correct data signals from said non-volatile memory means and storing said correct data signals in said dynamic memory in response to receiving said interrupt signals, whereby successive ones of said data signals are refreshed as a result of being read by said direct memory access controller and parity errors are corrected as a result of said recovery means storing correct versions of said data signals in said memory.
Claim 2
Dependent Claim
211 words
A circuit for refreshing, checking and correcting data signals stored in a dynamic memory, comprising: (a) a data bus for connection to said dynamic memory, (b) a direct memory access controller for connection to said memory and said data bus, for periodically reading successive ones of said data signals such that said data signals appear on said data bus, (c) a parity checking circuit, connected to said data bus, for detecting parity errors in said data signals and generating interrupt signals in response thereto, (d) recovery means connected to said data bus and said parity checking circuit, for receiving said interrupt signals and generating and storing correct versions of said data signals in said dynamic memory in response thereto, and (e) said recovery means being comprised of non-volatile memory means containing said correct versions of said data signals and means for retrieving said correct data signals from said non-volatile memory means and storing said correct data signals in said dynamic memory in response to receiving said interrupt signals, whereby successive ones of said data signals are refreshed as a result of being read by said direct memory access controller and parity errors are corrected as a result of said recovery means storing correct versions of said data signals in said memory.
Claim 3
Dependent Claim
26 words
A circuit as defined in claim 1, wherein said means for retrieving and storing said correct versions of said data signals is comprised of a microprocessor.
Claim 4
Dependent Claim
36 words
A circuit as defined in claim 2, further comprising a timer circuit for generating request signals to the direct memory access controller for causing said controller to periodically read said data signals stored in said memory.
Claim 5
Dependent Claim
16 words
A circuit as defined in claim 1 wherein said non-volatile memory means is a floppy disk.
Claim 6
Dependent Claim
15 words
A circuit as defined in claim 1 wherein said non-volatile memory means is an EPROM.
Claim 7
Dependent Claim
36 words
A circuit as defined in claim 1 further comprising a timer circuit for generating request signals to the direct memory access controller for causing said controller to periodically read said data signals stored in said memory.
Claim 8
Dependent Claim
36 words
A circuit as defined in claim 2, further comprising a timer circuit for generating request signals to the direct memory access controller for causing said controller to periodically read said data signals stored in said memory.
Claim 9
Dependent Claim
16 words
A circuit as defined in claim 2 wherein said non-volatile memory means is a floppy disk.
Claim 10
Dependent Claim
15 words
A circuit as defined in claim 2 wherein said non-volatile memory means is an EPROM.
Claim 11
Dependent Claim
169 words
A circuit tor refreshing, checking and correcting data signals stored in a dynamic memory, comprising: (a) a direct memory access controller for periodically reading successive ones of said data signals, (b) a parity checking circuit connected in a circuit to said direct memory access controller for detecting parity errors in said data signals read by said direct memory access controller and generating interrupt signals in response thereto, (c) non-volatile memory means for storing correct versions of said data signals, and (d) a microprocessor connected to said non-volatile memory means, said dynamic memory and said parity checking circuit for receiving said interrupt signals and reading said correct versions of said data signals from said non-volatile memory means and storing said correct versions in the dynamic memory in response thereto, whereby said data signals stored in the dynamic memory are refreshed in response to being read by said direct memory access controller and corrected in response to said microprocessor storing said correct versions of the data signals in said dynamic memory.
Claim 12
Dependent Claim
169 words
A circuit tor refreshing, checking and correcting data signals stored in a dynamic memory, comprising: (a) a direct memory access controller for periodically reading successive ones of said data signals, (b) a parity checking circuit connected in a circuit to said direct memory access controller for detecting parity errors in said data signals read by said direct memory access controller and generating interrupt signals in response thereto, (c) non-volatile memory means for storing correct versions of said data signals, and (d) a microprocessor connected to said non-volatile memory means, said dynamic memory and said parity checking circuit for receiving said interrupt signals and reading said correct versions of said data signals from said non-volatile memory means and storing said correct versions in the dynamic memory in response thereto, whereby said data signals stored in the dynamic memory are refreshed in response to being read by said direct memory access controller and corrected in response to said microprocessor storing said correct versions of the data signals in said dynamic memory.
Claim 13
Dependent Claim
31 words
A circuit as defined in claim 10, further comprised of timer means for generating a clock signal for transmission to said direct memory access controller in order to synchronize operation thereof.
Claim 14
Independent Claim
126 words
A method for refreshing, checking and correcting data signals stored in a dynamic memory, comprising the steps of: (a) periodically transferring data signals stored in successive locations of the dynamic memory to a non-existent peripheral, (b) detecting parity errors in said transferred data signals and generating interrupt signals in response thereto, (c) storing correct versions of said data signals in a non-volatile memory, and (d) receiving said interrupt signals and in response reading said correct versions of said data signals form said non-volatile memory and storing said correct versions in the dynamic memory, whereby said data signals are refreshed in response to being transferred to said non-existent peripheral and corrected in response to said correct versions of the data signals being stored in said dynamic memory.
Claim 15
Independent Claim
126 words
A method for refreshing, checking and correcting data signals stored in a dynamic memory, comprising the steps of: (a) periodically transferring data signals stored in successive locations of the dynamic memory to a non-existent peripheral, (b) detecting parity errors in said transferred data signals and generating interrupt signals in response thereto, (c) storing correct versions of said data signals in a non-volatile memory, and (d) receiving said interrupt signals and in response reading said correct versions of said data signals form said non-volatile memory and storing said correct versions in the dynamic memory, whereby said data signals are refreshed in response to being transferred to said non-existent peripheral and corrected in response to said correct versions of the data signals being stored in said dynamic memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-07-20 | 1991-01-19 | 1991-07-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-07-20 | 1995-01-19 | 1995-07-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-07-20 | 1999-01-19 | 1999-07-21 | $7700.00 | Window Closed / Lapsed |