Decoding digital data

Claim 3

A method according to claim 1, wherein said synchronizing code includes n bits and said step of checking the incoming digital data to locate the positions of said synchronizing codes uses a majority logic decision to achieve a single error correcting code in which a bit pattern having n-1 of its bits identical with the corresponsing bits of said synchronizing code is deemed to be said synchronizing code.

Claim 4

A method according to claim 1 wherein said address codes include an error detection and correction code, and said step of checking successive address codes to ascertain if said block address increases by one from one address code to the next is disabled if said error detection and correction code detects more than one error in the associated address code.

Claim 5

Apparatus for decoding incoming digital data provided at a high data rate from a digital tape video recorder or the like and which includes respective synchronizing codes and address codes associated with successive data blocks, the address codes comprising respective data block addresses which increase by one from data block to data block, the apparatus comprising: a synchronizing code decoder for checking the incoming digital data to locate the positions of said synchronizing code; an address comparison circuit for checking successive address codes to ascertain if said block address increases by one from one address code to the next; and means operative if said block address increases by one from one address code to the next for aligning said incoming data using synchronizing codes for subsequent decoding of said data blocks, to insure correct and rapid identification of the incoming synchronizing and address codes while minimizing redundant bits.

Claim 6

Apparatus for decoding incoming digital data provided at a high data rate from a digital tape video recorder or the like and which includes respective synchronizing codes and address codes associated with successive data blocks, the address codes comprising respective data block addresses which increase by one from data block to data block, the apparatus comprising: a synchronizing code decoder for checking the incoming digital data to locate the positions of said synchronizing code; an address comparison circuit for checking successive address codes to ascertain if said block address increases by one from one address code to the next; and means operative if said block address increases by one from one address code to the next for aligning said incoming data using synchronizing codes for subsequent decoding of said data blocks, to insure correct and rapid identification of the incoming synchronizing and address codes while minimizing redundant bits.

Claim 7

Apparatus according to claim 4, wherein said synchronizing code includes n bits and said synchronizing code decoder comprises majority logic operative to achieve a single error correcting code in which a bit pattern having n-1 of its bits identical with the corresponding bits of said synchronizing code is deemed to be said synchronizing code.

Claim 8

Apparatus according to claim 4, wherein said address codes include an error detection and correction code, and said means for aligning is disabled if said error detection and correction code detects more than one error in the associated address code.

Claim 9

Apparatus according to claim 6 wherein said error detection and correction code makes use of four bit to eight bit coding of said block addresses.

Claim 10

Apparatus according to claim 4, wherein said means for aligning further includes means for inserting locally generated synchronizing and address codes into said aligned incoming digital data, said means for inserting being locked to the incoming synchronizing codes located by said synchronizing code decoder and to said incoming address codes supplied to said address comparison circuit.

Claim 11

Apparatus according to claim 4 wherein said digital data is video data.