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EP0093527A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Sequential data block address processing circuits

Assignee: Sony Corp
•
Filing: 1983-04-15
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Granted: —
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Expires: 2003-04-15
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Abstract

Abstract A sequential data block address processing circuit for deriving address signals in dependence on incoming data representing, for example, a digital television signal and formed by sequential blocks of data each including a block address which changes cyclically, from block to block and which is formed of three address words respectively representing block, line and segment numbers which change cyclically, the circuit comprising a read-only memory (12) operative for each incoming block address to increment the block number and if this incrementing involves a carry to increment the line number and so on up to the segment number, and further operative for each incoming block address to form a predicted next block address which is formed of three address words each representing the respective block, line or segment number or incremented number as appropriate, and a comparator (9) to compare each predicted next block address with the next incoming block address and to supply a correct address indication only if there is identity between one or more of the compared block addresses, and an address regenerator (22) which is locked to the block addresses in the incoming data if, and only if, the comparator (9) is indicating identity between one or more of the compared block addresses.

Inventors

  • 👤 James Hedley Wilkinson

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-27 16:49
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/76; H04N5/91; H04N5/93; H04N5/935; G; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B27/00; G11B27/10; G11B27/102; G11B27/107; G11B27/36

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 209 words
A sequential data block address processing circuit for deriving address signals in dependence on incoming data, the circuit comprising: means (1, 3 to 8) to receive incoming sequential blocks of data each including a block address which changes cyclically from block to block and which is formed of a plurality of address words each representing a respective number which changes cyclically; characterised by: means (12, 13) operative for each incoming block address to increment the number represented by the address word of said block address which represents the least significant said number and if said incrementing involves a carry to increment the number represented by the address word of said block address which represents the next most significant said number, and so on up to the address word of said block which represents the most significant said number, and further operative for each incoming block address to form a predicted block address which is formed of a plurality of address words each representing the respective said number or incremented number as appropriate; and means (9) to compare each predicted next block address with the next incoming block address and to supply a correct address indication only if there is identity between one or more of the compared block addresses.
Claim 2
Dependent Claim 209 words
A sequential data block address processing circuit for deriving address signals in dependence on incoming data, the circuit comprising: means (1, 3 to 8) to receive incoming sequential blocks of data each including a block address which changes cyclically from block to block and which is formed of a plurality of address words each representing a respective number which changes cyclically; characterised by: means (12, 13) operative for each incoming block address to increment the number represented by the address word of said block address which represents the least significant said number and if said incrementing involves a carry to increment the number represented by the address word of said block address which represents the next most significant said number, and so on up to the address word of said block which represents the most significant said number, and further operative for each incoming block address to form a predicted block address which is formed of a plurality of address words each representing the respective said number or incremented number as appropriate; and means (9) to compare each predicted next block address with the next incoming block address and to supply a correct address indication only if there is identity between one or more of the compared block addresses.
Claim 3
Dependent Claim 79 words
A circuit according to claim 1 further comprising an address counter arrangement (22) to which said incoming data is supplied, and which generates said block addresses which change cyclically from block to block, and means to supply the result of said comparison to said address counter arrangement (22) and to lock said generation of said block address to the block addresses in said incoming data only when said correct address indication is received by said address counter arrangement (22).
Claim 4
Dependent Claim 18 words
A circuit according to claim 1 or claim 2 wherein said incoming data represents a digital television signal.
Claim 5
Dependent Claim 65 words
A circuit according to claim 3 wherein said plurality is three and said numbers represented by said address words correspond respectively to blocks, each of which represents a fractional part of a horizontal line of the television signal, to horizontal lines of the television signal, and to segments, each of which represents a fractional part or the whole of a field of the television signal.
Claim 6
Dependent Claim 26 words
A circuit according to any one of the preceding claims wherein said means effecting the incrementing and predicting of block addresses comprises a read-only memory (12).
Claim 7
Dependent Claim 44 words
A circuit according to any one of the preceding claims wherein said means (9) to compare each predicted next block address with the next incoming block address supplies a said correct address indication only if there is identity between three successive compared block addresses.

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