Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
273 words
An autosync circuit for synchronizing decoders for digital communications which use block codes, and which does not require a sync pattern in the digital data signal but uses a plurality of parity bits in each digital word, said apparatus comprising, a plurality of word length shift registers connected in series into which the serial digital data signal is shifted using an external clock from the data source and said shift registers having an output from each stage of the shift registers, a means for checking the parity of the bit group for each parity bit in the digital word in the first of said shift registers, using the outputs from each stage of said first shift register, and a means for combining the output of said parity checking means so as to produce a single signal output signifying that the parity is true for all parity bit groups of said digital word in the first shift register, means for checking the parity of each bit group for each parity bit in each of the other digital words in each of the plurality of said shift registers with means for combining the outputs of said parity checking means so as to produce a single output for each digital word signifying that the parity is true for all parity bit groups of the digital word. a means for combining the outputs of said parity checking means for each of the plurality of digital words in the said plurality of shift registers, said signal signifying that the parity is true for all parity groups of the said digital words, and said signal being the synchronizing signal.
Claim 2
Dependent Claim
273 words
An autosync circuit for synchronizing decoders for digital communications which use block codes, and which does not require a sync pattern in the digital data signal but uses a plurality of parity bits in each digital word, said apparatus comprising, a plurality of word length shift registers connected in series into which the serial digital data signal is shifted using an external clock from the data source and said shift registers having an output from each stage of the shift registers, a means for checking the parity of the bit group for each parity bit in the digital word in the first of said shift registers, using the outputs from each stage of said first shift register, and a means for combining the output of said parity checking means so as to produce a single signal output signifying that the parity is true for all parity bit groups of said digital word in the first shift register, means for checking the parity of each bit group for each parity bit in each of the other digital words in each of the plurality of said shift registers with means for combining the outputs of said parity checking means so as to produce a single output for each digital word signifying that the parity is true for all parity bit groups of the digital word. a means for combining the outputs of said parity checking means for each of the plurality of digital words in the said plurality of shift registers, said signal signifying that the parity is true for all parity groups of the said digital words, and said signal being the synchronizing signal.
Claim 3
Dependent Claim
49 words
An autosync circuit as defined in claim 1 and including, a counter means which is reset by said synchronizing signal from said means to combine the parity checking signal for each of the digital words of said shift registers, and said counter output being a synchronizing signal each word.
Claim 4
Dependent Claim
130 words
An autosync circuit as defined in claim 1 and including, a means to combine the outputs of said parity checking means for each of the digital words of said shift registers so that the output of said combining means is a signal signifying that the parity is true for all parity bit groups of at least one digital word, and said signal being called a sync inhibit signal for reference, a circuit means to combine said synchronizing signal and said sync inhibit signal such that the synchronizing signal output of said circuit means is inhibited for one word period for each sync inhibit signal input to said circuit means, said circuit means prevents false sync signal output for one word period each sync inhibit signal input to said circuit means.