Patent US4680735A successfully refreshed from Google Patents.
US4680735A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Toshiba Corp
•
Filing: 1985-07-26
•
Granted: 1987-07-14
•
Expires: 2005-07-26
Abstract
Abstract A sense amplifier comprising a flip-flop circuit is provided for each bit line pair. A first transistor is connected between the flip-flop circuit and V DD power source. A second transistor is connected between the flip-flop circuit and ground. A control signal for controlling the active state of the flip-flop is applied to the gate of the first transistor, with a minimum time delay. The control signal is also applied to the gate of the second transistor, with a time delay corresponding to that caused by the word line. The timing for rendering each flip-flop circuit in the active state is substantially coincident with the optimum timing of a change in potential on each corresponding bit line.
Inventors
- 👤 Junichi Miyamoto
- 👤 Jun-ichi Tsujimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 10:13
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/14; G11C5/00; G11C5/06; G11C5/063; G11C5/14; G11C7/00; G11C7/06; G11C7/065
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
178 words
A semiconductor memory device comprising: a plurality of bit line pairs, the bit lines of each pair being respectively connected to a memory cell and to a dummy cell which are respectively selected by signals derived from word lines; a plurality of means for sensing data by amplifying a potential difference between each pair of bit lines; a plurality of first transistors each having a gate connected between said data-sensing means and a power source for receiving at the respective gates, with a minimum time delay, a control signal to control the active state of each said data-sensing means; and a plurality of second transistors each having a gate connected between said data-sensing means and the power source respectively, said second transistors being connected in series with said first transistors, and for receiving at the respective gates of said second transistors said control signal with predetermined time delays, each of the predetermined time delays being substantially equal to the time delay of a signal on the word line connected to the memory cell associated with the data-sensing means.
Claim 2
Dependent Claim
178 words
A semiconductor memory device comprising: a plurality of bit line pairs, the bit lines of each pair being respectively connected to a memory cell and to a dummy cell which are respectively selected by signals derived from word lines; a plurality of means for sensing data by amplifying a potential difference between each pair of bit lines; a plurality of first transistors each having a gate connected between said data-sensing means and a power source for receiving at the respective gates, with a minimum time delay, a control signal to control the active state of each said data-sensing means; and a plurality of second transistors each having a gate connected between said data-sensing means and the power source respectively, said second transistors being connected in series with said first transistors, and for receiving at the respective gates of said second transistors said control signal with predetermined time delays, each of the predetermined time delays being substantially equal to the time delay of a signal on the word line connected to the memory cell associated with the data-sensing means.
Claim 3
Dependent Claim
36 words
A semiconductor memory device according to claim 1, in which a capacitance formed at the gate of each of said second transistors is substantially equal to that of the memory cell connected to said word line.
Claim 4
Dependent Claim
33 words
A semiconductor memory device according to claim 1, in which said first transistors are each arranged closer to said power source, and said second transistors are each arranged closer to said data-sensing means.
Claim 5
Dependent Claim
20 words
A semiconductor memory device according to claim 1, in which each of said data sensing means include a flip-flop circuit.
Claim 6
Dependent Claim
169 words
A semiconducting device comprising: a plurality of bit line pairs, each pair of bit lines being respectively connected to a memory cell and to a dummy cell which are respectively selected by signals derived from word lines; a plurality of means for sensing data by amplifying a potential difference between each pair of bit lines; a first transistor having a gate connected between said data-sensing means and the power source for receiving at the gate, with a minimum time delay, a control signal to control the active state of each of said data-sensing means; and a plurality of second transistors each having a gate connected between said data-sensing means and the power source respectively, said second transistor being connected in series to said first transistor, and for receiving, at the respective gates, said control signal with predetermined time delays, each of the predetermined time delays being substantially equal to the time delay of a signal on the word line connected to the memory cell associated with the data-sensing means.
Claim 7
Dependent Claim
169 words
A semiconducting device comprising: a plurality of bit line pairs, each pair of bit lines being respectively connected to a memory cell and to a dummy cell which are respectively selected by signals derived from word lines; a plurality of means for sensing data by amplifying a potential difference between each pair of bit lines; a first transistor having a gate connected between said data-sensing means and the power source for receiving at the gate, with a minimum time delay, a control signal to control the active state of each of said data-sensing means; and a plurality of second transistors each having a gate connected between said data-sensing means and the power source respectively, said second transistor being connected in series to said first transistor, and for receiving, at the respective gates, said control signal with predetermined time delays, each of the predetermined time delays being substantially equal to the time delay of a signal on the word line connected to the memory cell associated with the data-sensing means.
Claim 8
Dependent Claim
36 words
A semiconductor memory device according to claim 5, in which a capacitance formed at the gate of each of said second transistors is substantially equal to that of the memory cell connected to said word line.
Claim 9
Dependent Claim
32 words
A semiconductor memory device according to claim 5, in which said first transistor is arranged closer to said power source, and said second transistors are each arranged closer to said data-sensing means.
Claim 10
Dependent Claim
19 words
A semiconductor memory device according to claim 5, in which each of said data-sending means includes a flip-flop circuit.
References Cited (Backward Citations)
US4169233A
Cited
US4558241A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-07-13 | 1991-01-12 | 1991-07-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-07-13 | 1995-01-12 | 1995-07-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-07-13 | 1999-01-12 | 1999-07-14 | $7700.00 | Window Closed / Lapsed |