Wired-AND FET logic gate

Claim 2

A logic circuit comprising: a plurality of wired-AND input circuits, each of which has a single pull-up field-effect transistor (FET) and a single input terminal connectable directly to a plurality of input signal lines to be logically ANDed together, the single input terminal being connectable to the plurality of input signal lines without any circuit elements being interposed between the input terminal and the plurality of input signal lines; a FET output circuit having a common gate circuit and multiple independent drain output lines, which are connectable directly to input terminals of similar logic circuits, the multiple independent drain output lines being connectable to the input terminals of similar logic circuits without any circuit elements being interposed between the drain output lines and the input terminals; and circuit means for logically ORing the plurality of wired-AND input circuits and applying the resultant signal to the gate circuit of the FET output circuit; wherein the FET output circuit acts as a voltage pull-down circuit when one or more of the outputs is applied to the input terminals of similar logic circuits, thereby allowing the one or more outputs to be applied to the input terminals of the similar logic circuits without any circuit elements being interposed between the one or more outputs and the input terminals, thus providing a logic circuit with fewer parts, low power dissipation and small time delays.

Claim 3

A logic circuit as set forth in claim 1, wherein the circuit means includes: a plurality of diodes, for coupling each of the plurality of input circuits to a common junction point; an additional diode connected between the common junction point and the gate circuit of the FET output circuit; and a pull-down FET connected between the gate circuit of the FET output circuit and a voltage source.

Claim 4

A logic circuit comprising: a plurality of wired-AND input circuits, each of which has a single pull-up field-effect transistor (FET) and a single input terminal connectable directly to a plurality of input signal lines to be logically ANDed together, all of the pull-up FET's being connected to a signal power supply and the single input terminal being connectable to the plurality of input signal lines without any circuit elements being interposed between the input terminal and the plurality of input signal lines; a FET output circuit having a common gate circuit and multiple independent drain output lines, which are connectable directly to input terminals of similar logic circuits, the multiple independent drain output lines being connectable to the input terminals of similar logic circuits without any circuit elements being interposed between the drain output lines and the input terminals; a plurality of forward-biased diodes, for coupling each of the plurality of input circuits to a common junction point; an additional diode connected between the common junction point and the gate circuit of the FET output circuit; and a pull-down FET connected between the gate circuit of the FET output circuit and a negative voltage source; wherein the FET output circuit acts as a voltage pull-down circuit when one or more of the outputs is applied to the input terminals of similar logic circuits, thereby allowing the one or more outputs to be applied to the input terminals of the similar logic circuits without any circuit elements being interposed between the one or more outputs and the input terminals, thus providing a logic circuit with fewer parts, low power dissipation and small time delays, and wherein each wired-AND input circuit performs the AND of its multiple inputs, the resultant set of ANDed signals being ORed together at the junction point, and the result inverted prior to output.

Claim 5

A logic circuit comprising: a plurality of wired-AND input circuits, each of which has a single pull-up field-effect transistor (FET) and a single input terminal connectable directly to a plurality of input signal lines to be logically ANDed together, all of the pull-up FET's being connected to a signal power supply and the single input terminal being connectable to the plurality of input signal lines without any circuit elements being interposed between the input terminal and the plurality of input signal lines; a FET output circuit having a common gate circuit and multiple independent drain output lines, which are connectable directly to input terminals of similar logic circuits, the multiple independent drain output lines being connectable to the input terminals of similar logic circuits without any circuit elements being interposed between the drain output lines and the input terminals; a plurality of forward-biased diodes, for coupling each of the plurality of input circuits to a common junction point; an additional diode connected between the common junction point and the gate circuit of the FET output circuit; and a pull-down FET connected between the gate circuit of the FET output circuit and a negative voltage source; wherein the FET output circuit acts as a voltage pull-down circuit when one or more of the outputs is applied to the input terminals of similar logic circuits, thereby allowing the one or more outputs to be applied to the input terminals of the similar logic circuits without any circuit elements being interposed between the one or more outputs and the input terminals, thus providing a logic circuit with fewer parts, low power dissipation and small time delays, and wherein each wired-AND input circuit performs the AND of its multiple inputs, the resultant set of ANDed signals being ORed together at the junction point, and the result inverted prior to output.

Claim 6

A logic circuit as set forth in claim 3, wherein: all of the FET's operate in the depletion mode.

Claim 7

A logic circuit as set forth in claim 3, wherein: the FET output circuit includes multiple FET's having gates connected in common to a single gate terminal, sources connected together to ground, and drain terminals that form the multiple outputs.