Thermoplastic plug method of fabricating an integrated circuit package having bonding pads in a stepped cavity

Claim 1

A method of fabricating an integrated circuit package prior to the placement of a circuit chip therein, said method including the steps of: assembling a stack which is comprised of a plurality of superposed thin flat epozy-glass layers, adhesive layers between said epoxy-glass layers, a staircase-shaped cavity which extends from an outer epoxy-glass layer of said stack to an internal epoxy-glass layer of said stack and goes parallel along a portion of the flat upper surface of said internal epoxy-glass layer and then penetrates through it, and conductors on said internal epoxy-glass layer including bonding pads on said flat upper surface portion; inserting into said cavity a thermoplastic plug which is coated with a film of a release material that resists sticking to said epoxy-glass and said adhesive, and which differs from the shape of said cavity by predetermined tolerances and extends over a larger area outside the cavity; laminating said stack, while said plug is in said cavity, at a temperature and pressure which causes said plug to soften and conform to the exact shape of said cavity, without sticking in said cavity, and thereby dam said adhesive from flowing onto said bonding pads on said flat upper surface portion; and removing said thermoplastic plug from said cavity subsequent to said laminating step.

Claim 2

A method of fabricating an integrated circuit package prior to the placement of a circuit chip therein, said method including the steps of: assembling a stack which is comprised of a plurality of superposed thin flat epozy-glass layers, adhesive layers between said epoxy-glass layers, a staircase-shaped cavity which extends from an outer epoxy-glass layer of said stack to an internal epoxy-glass layer of said stack and goes parallel along a portion of the flat upper surface of said internal epoxy-glass layer and then penetrates through it, and conductors on said internal epoxy-glass layer including bonding pads on said flat upper surface portion; inserting into said cavity a thermoplastic plug which is coated with a film of a release material that resists sticking to said epoxy-glass and said adhesive, and which differs from the shape of said cavity by predetermined tolerances and extends over a larger area outside the cavity; laminating said stack, while said plug is in said cavity, at a temperature and pressure which causes said plug to soften and conform to the exact shape of said cavity, without sticking in said cavity, and thereby dam said adhesive from flowing onto said bonding pads on said flat upper surface portion; and removing said thermoplastic plug from said cavity subsequent to said laminating step.

Claim 7

A method of fabricating an integrated circuit package prior to the placement of a circuit chip therein, said method including the steps of: assembling a stack which is comprised of a plurality of superposed thin flat dielectric layers, adhesive between said dielectric layers, a cavity which extends from one outer dielectric layer of said stack through an internal dielectric layer of said stack and is shaped to expose a portion of the flat upper surface of said internal dielectric layer, and conductors on said internal dielectric layer including bonding pads on said exposed flat upper surface portion; inserting into said cavity a snugly fitting thermoplastic plug which extends outside the cavity and which resists sticking to said dielectric layers and said bonding pads; permanently joining the layers of said stack by compressing the layers of said stack while said plug is inserted in said cavity at a temperature and pressure which causes said plug to soften and fill any voids in said cavity; and removing said plug from said cavity subsequent to said joining step.

Claim 8

A method of fabricating an integrated circuit package prior to the placement of a circuit chip therein, said method including the steps of: assembling a stack which is comprised of a plurality of superposed thin flat dielectric layers, adhesive between said dielectric layers, a cavity which extends from one outer dielectric layer of said stack through an internal dielectric layer of said stack and is shaped to expose a portion of the flat upper surface of said internal dielectric layer, and conductors on said internal dielectric layer including bonding pads on said exposed flat upper surface portion; inserting into said cavity a snugly fitting thermoplastic plug which extends outside the cavity and which resists sticking to said dielectric layers and said bonding pads; permanently joining the layers of said stack by compressing the layers of said stack while said plug is inserted in said cavity at a temperature and pressure which causes said plug to soften and fill any voids in said cavity; and removing said plug from said cavity subsequent to said joining step.

Claim 15

A method of fabricating an integrated circuit package prior to the placement of a circuit chip therein, said method including the steps of: assembling a stack which is comprised of a plurality of superposed thin flat green-ceramic layers, a cavity which extends from one outer green-ceramic layer of said stack through an internal green-ceramic layer of said stack and is shaped to expose a portion of the flat upper surface of said internal green-ceramic layer, and conductors on said internal green-ceramic layer including bonding pads on said exposed flat upper surface portion; inserting into said cavity a snugly fitting thermoplastic plug which extends outside the cavity and which resists sticking to said green-ceramic layers and said bonding pads; permanently joining the layers of said stack by compressing the layers of said stack while said plug is inserted in said cavity at a temperature and pressure which causes said plug to soften and fill any voids in said cavity; and removing said plug from said cavity subsequent to said joining step.

Claim 16

A method of fabricating an integrated circuit package prior to the placement of a circuit chip therein, said method including the steps of: assembling a stack which is comprised of a plurality of superposed thin flat green-ceramic layers, a cavity which extends from one outer green-ceramic layer of said stack through an internal green-ceramic layer of said stack and is shaped to expose a portion of the flat upper surface of said internal green-ceramic layer, and conductors on said internal green-ceramic layer including bonding pads on said exposed flat upper surface portion; inserting into said cavity a snugly fitting thermoplastic plug which extends outside the cavity and which resists sticking to said green-ceramic layers and said bonding pads; permanently joining the layers of said stack by compressing the layers of said stack while said plug is inserted in said cavity at a temperature and pressure which causes said plug to soften and fill any voids in said cavity; and removing said plug from said cavity subsequent to said joining step.