Double polysilicon integrated circuit process

Claim 1

A double polysilicon integrated circuit processing method comprising: (i) taking a silicon wafer; (ii) forming field oxide regions therein; (iii) forming a gate oxide layer over a device well region, said device well region having source, gate and capacitor areas; (iv) depositing a first polysilcon layer over the gate oxide layer; (v) etching the polysilicon to form a transistor gate over said gate area; (vi) forming a second oxide layer over the gate and the surrounding device region; (vii) depositing a second polysilicon layer over the second oxide layer; (viii) etching the second polysilicon layer to leave polysilicon over said capacitor area; and (ix) in a single implantation step, implanting ions through said second oxide layer into said source area to form a transistor source and through said oxide and second polysilicon layers to define one side of a capacitor at said capacitor area, said second level polysilicon at the capacitor area functioning as an opposed side of the capacitor, and the second oxide layer at the capacitor area functioning as a capacitor dielectric, the junction depth and concentration of ions in the capacitor area being less than the junction depth and concentration of ions in the source area.