US4679213A
Expired / Lapsed
US
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Asynchronous queue system
Assignee: SUTHERLAND SPROULL AND ASSOCIATES Inc
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Filing: 1985-01-08
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Granted: 1987-07-07
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Expires: 2005-01-08
Abstract
Abstract A queue form of asynchronous register is disclosed with signal paths commonly carrying elements of both data and control. Binaries are intercoupled in two sequences and are individually cross coupled to register "one" bits in one sequence and "zero" bits in the other. Bits are manifest by signal level changes. Individual binaries are driven by logic to accomplish an operational rule based on the states of neighboring binaries in both sequences. Each binary in each sequence is controlled by the states of the predecessor and successor in its sequence and the predecessor and successor of its associated binary in the other sequence. Specifically, if predecessor and successor binaries in a sequence are in different states, and predecessor and successor binaries of an associated binary in the other sequence are in the same state, the state of the predecessor is to be taken.
Inventors
- 👤 Ivan E. Sutherland
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 19:31
CPC Classifications
G; G11; G11C; G11C19/00
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
80 words
A register for binary digital data comprising: a first series of binaries for registering one binary digit; a second series of binaries individually associated with binaries of said first series and for registering another binary digit; control means intercoupling said first and second series of binaries for causing a binary to assume the state of its predecessor when its predecessor and successor are in different states and the predecessor and successor of its associated binary are in the same state.
Claim 2
Dependent Claim
80 words
A register for binary digital data comprising: a first series of binaries for registering one binary digit; a second series of binaries individually associated with binaries of said first series and for registering another binary digit; control means intercoupling said first and second series of binaries for causing a binary to assume the state of its predecessor when its predecessor and successor are in different states and the predecessor and successor of its associated binary are in the same state.
Claim 3
Dependent Claim
19 words
A register according to claim 1 wherein said control means intercoupling said binaries actuates said binaries to operate asynchronously.
Claim 4
Dependent Claim
25 words
A register according to claim 1 wherein said control means intercoupling said binaries comprises means for transferring data between said binaries by signal level changes.
Claim 5
Dependent Claim
29 words
A register according to claim 1 further including input means for supplying "ones" digits to said first series of binaries and "zeros" digits to said second series of binaries.
Claim 6
Dependent Claim
140 words
A queue register for binary bits comprising: input means for supplying first binary bits to a first path and second binary bits to a second path; a first plurality of binaries interconnected in a sequence and coupled to receive said first binary bits from said first path; a second plurality of binaries interconnected in a sequence and coupled to receive said second binary bits from said second path; and means intercoupling said pluralities of binaries in associated means relationship for inhibiting progression of binary bits in said sequences to preserve an orderly registration of binary bits in said first and second pluralities and to allow propagation of a state signal into a binary when the successor to said binary is in an opposed state to the state signal and the binaries contiguous to an associated binary are in similar states.
Claim 7
Dependent Claim
140 words
A queue register for binary bits comprising: input means for supplying first binary bits to a first path and second binary bits to a second path; a first plurality of binaries interconnected in a sequence and coupled to receive said first binary bits from said first path; a second plurality of binaries interconnected in a sequence and coupled to receive said second binary bits from said second path; and means intercoupling said pluralities of binaries in associated means relationship for inhibiting progression of binary bits in said sequences to preserve an orderly registration of binary bits in said first and second pluralities and to allow propagation of a state signal into a binary when the successor to said binary is in an opposed state to the state signal and the binaries contiguous to an associated binary are in similar states.
Claim 8
Dependent Claim
18 words
A register according to claim 5 wherein said input means supplies said bits represented as signal level changes.
Claim 9
Dependent Claim
14 words
A register according to claim 5 wherein said means intercoupling comprises an asynchronous structure.
Claim 10
Dependent Claim
70 words
A register according to claim 5 wherein said means for inhibiting allows propagation of a state signal into a binary only if the successor to said binary is in an opposed state to the state signal and the binaries contiguous to an associated binary are in similar states, wherein said input means supplies said bits represented as signal level changes, and furthermore wherein said means intercoupling comprises an asynchronous structure.
Claim 11
Dependent Claim
33 words
A register according to claim 1 wherein said control means intercouples said binaries to operate asynchronously and wherein said control means includes means for transferring data between said binaries by signal level changes.
Claim 12
Dependent Claim
29 words
A register according to claim 9 further including input means for supplying "ones" digits to said first series of binaries and "zeros" digits to said second series of binaries.
Claim 13
Dependent Claim
160 words
A queue register for binary bits comprising: input means for supplying first binary bits to a first path and second binary bits to a second path said bits being represented as signal level changes; a first plurality of binaries interconnected in a sequence and coupled to receive and respond to said first binary bits from said first path; a second plurality of binaries interconnected in a sequence and coupled to receive and respond to said second binary bits from said second path; means intercoupling said binaries between said first and second pluralities to provide pairs of binaries; and means for selectively inhibiting progression of binary bits in said sequences of binaries to preserve an orderly registration of binary bits in said first and second pluralities, said means for inhibiting allowing progression of binary bits to a sequence binary under control of binaries contiguous to said sequence binary and binaries contiguous to the binary in pair relationship with said sequence binary.
Claim 14
Dependent Claim
160 words
A queue register for binary bits comprising: input means for supplying first binary bits to a first path and second binary bits to a second path said bits being represented as signal level changes; a first plurality of binaries interconnected in a sequence and coupled to receive and respond to said first binary bits from said first path; a second plurality of binaries interconnected in a sequence and coupled to receive and respond to said second binary bits from said second path; means intercoupling said binaries between said first and second pluralities to provide pairs of binaries; and means for selectively inhibiting progression of binary bits in said sequences of binaries to preserve an orderly registration of binary bits in said first and second pluralities, said means for inhibiting allowing progression of binary bits to a sequence binary under control of binaries contiguous to said sequence binary and binaries contiguous to the binary in pair relationship with said sequence binary.
Claim 15
Dependent Claim
14 words
A register according to claim 11 wherein said means intercoupling comprises an asynchronous structure.
Claim 16
Dependent Claim
74 words
A register according to claim 11 wherein said means for selectively inhibiting allows propagation of a state signal into a sequence binary when the successor to said sequence binary is in an opposed state to the state signal and the binaries contiguous to said binary in pair relationship are in similar states, wherein said input means supplies said bits represented as signal level changes, and furthermore wherein said mcans intercoupling comprises an asynchronous structure.
Claim 17
Dependent Claim
29 words
A register according to claim 11 further including input means for supplying "ones" digits to said first series of binaries and "zeros" digits to said second series of binaries.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-07-06 | 1991-01-05 | 1991-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-07-06 | 1995-01-05 | 1995-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-07-06 | 1999-01-05 | 1999-07-07 | $7700.00 | Window Closed / Lapsed |