Fault detection algorithm for successive-approximation A/D converters

Claim 3

The method according to claim 1 wherein said step of injecting an offset includes injecting a controlled current thereto.

Claim 4

The method according to claim 1 wherein said step of injecting an offset includes injecting a controlled voltage thereto.

Claim 5

The method according to claim 1, wherein the step of verifying the output shift includes comparing the observed output logic level of the comparator to the alternating sign of said injected offset and outputting an alarm out signal if said output does not correspond to the expected output logic level thereof.

Claim 6

The method according to claim 1, wherein said step of injecting into an input includes injecting into a positive input of the comparator.

Claim 7

The method according to claim 1, wherein said step of injecting into an input includes injecting into a negative input of the comparator.

Claim 8

Apparatus for self-testing at high speed a successive approximation A/D converter having a relatively long conversion cycle and including at least a track-and-hold circuit which drives a loop consisting of a comparator, a successive approximation register, a D/A converter, and controlled by a timing source, the apparatus comprising: offset generating means coupled to an input of the comparator and to the timing source of said A/D converter for injecting into an input of said comparator at the end of each conversion cycle an offset having a sign that alternates for each conversion cycle and a small magnitude that slightly exceeds a level discernible as one least significant bit; and verification means coupled to the output of said comparator and having an alarm output for indicating when the observed output logic level fails to correspond to the expected output logic level which is dependent on the sign of said injected offset signal, thereby achieving self-test of virtually all of the A/D converter elements over a wide range of input values in a fraction of an entire conversion cycle.

Claim 9

Apparatus for self-testing at high speed a successive approximation A/D converter having a relatively long conversion cycle and including at least a track-and-hold circuit which drives a loop consisting of a comparator, a successive approximation register, a D/A converter, and controlled by a timing source, the apparatus comprising: offset generating means coupled to an input of the comparator and to the timing source of said A/D converter for injecting into an input of said comparator at the end of each conversion cycle an offset having a sign that alternates for each conversion cycle and a small magnitude that slightly exceeds a level discernible as one least significant bit; and verification means coupled to the output of said comparator and having an alarm output for indicating when the observed output logic level fails to correspond to the expected output logic level which is dependent on the sign of said injected offset signal, thereby achieving self-test of virtually all of the A/D converter elements over a wide range of input values in a fraction of an entire conversion cycle.

Claim 10

The apparatus according to claim 7, wherein offset generating means for injecting an offset signal into an input of the comparator comprises an offset inject circuit controlled by an offset/test command from said timing source.

Claim 11

The apparatus according to claim 7, wherein verification means for indicating when the observed output logic level fails to correspond to the expected output logic level which is dependent on the alternating sign of said injected offset signal comprises comparison means and alarm output generating means for indicating when the observed output logic level fails to correspond to the expected output logic level.

Claim 12

The apparatus according to claim 7, wherein offset generating means couples to a positive input of the comparator.

Claim 13

The apparatus according to claim 7, wherein offset generating means couples to a negative input of the comparator.

Claim 14

A successive approximation A/D converter circuit having high speed self-testing capability, the circuit comprising in combination: a track-and-hold circuit having an analog input; an A/D conversion loop which includes a comparator that electrically couples to an output of said track-and-hold circuit and which has a plurality of digital outputs; and a fault detect circuit electrically coupled to said comparator at its input for injecting thereto an offset having a sign that alternates for each conversion cycle and having a small magnitude that slightly exceeds a level discernible as one least significant bit, and coupled to said comparator at its output for verifying that said loop is responsive to an offset affecting a converged value within said loop, said fault detect circuit thereby providing an alarm output signal when the observed output logic level of said comparator fails to correspond to the expected output logic level thereof.

Claim 15

A successive approximation A/D converter circuit having high speed self-testing capability, the circuit comprising in combination: a track-and-hold circuit having an analog input; an A/D conversion loop which includes a comparator that electrically couples to an output of said track-and-hold circuit and which has a plurality of digital outputs; and a fault detect circuit electrically coupled to said comparator at its input for injecting thereto an offset having a sign that alternates for each conversion cycle and having a small magnitude that slightly exceeds a level discernible as one least significant bit, and coupled to said comparator at its output for verifying that said loop is responsive to an offset affecting a converged value within said loop, said fault detect circuit thereby providing an alarm output signal when the observed output logic level of said comparator fails to correspond to the expected output logic level thereof.

Claim 16

The circuit according to claim 12, wherein said A/D conversion loop comprises in combination: a comparator having an output and a pair of inputs; a successive approximation register electrically coupled to said comparator output and having a plurality of outputs; a D/A converter coupled to said plurality of outputs from the successive approximation register and having an output coupled to an input of said comparator; and a timing source having a first output coupled to said successive approximation register, a second output coupled to said track-and-hold circuit, and a third output coupled to said fault detect circuit for controlling the timing of the successive approximation converter.

Claim 17

The circuit according to claim 12, wherein said fault detect circuit couples to a positive input of the comparator.

Claim 18

The circuit according to claim 12, wherein said fault detect circuit couples to a negative input of the comparator.

Claim 19

A fault detect circuit for self-testing at high speed a successive approximation A/D converter having a relatively long conversion cycle and including at least a track-and-hold circuit which drives a loop consisting of a comparator, a successive approximation register, a D/A converter, and a timing source, the fault detect circuit comprising in combination: an offset inject circuit having logic elements for control and coupled to an input of the comparator and to the timing source of said A/D converter for injecting into an input of said comparator at the end of each conversion cycle an offset having a sign that alternates for each conversion cycle and a small magnitude that slightly exceeds a level discernible as one least significant bit; and a verification circuit coupled to the output of said comparator and having an alarm output for indicating when the observed output logic level fails to correspond to the expected output logic level which is dependent on the sign of said injected offset signal, thereby achieving self-test of virtually all of the A/D converter elements over a wide range of input values in a fraction of an entire conversion cycle.

Claim 20

A fault detect circuit for self-testing at high speed a successive approximation A/D converter having a relatively long conversion cycle and including at least a track-and-hold circuit which drives a loop consisting of a comparator, a successive approximation register, a D/A converter, and a timing source, the fault detect circuit comprising in combination: an offset inject circuit having logic elements for control and coupled to an input of the comparator and to the timing source of said A/D converter for injecting into an input of said comparator at the end of each conversion cycle an offset having a sign that alternates for each conversion cycle and a small magnitude that slightly exceeds a level discernible as one least significant bit; and a verification circuit coupled to the output of said comparator and having an alarm output for indicating when the observed output logic level fails to correspond to the expected output logic level which is dependent on the sign of said injected offset signal, thereby achieving self-test of virtually all of the A/D converter elements over a wide range of input values in a fraction of an entire conversion cycle.

Claim 21

The fault detect circuit according to claim 16, wherein said offset inject circuit comprises a bipolar current source including two transistors, a divide-by-two flip-flop, and logic gates to permit control from the timing source.

Claim 22

The fault detect circuit according to claim 16, wherein said verification circuit comprises a one-bit digital discriminator such as an exclusive-OR gate, a latch formed by a flip-flop, and a plurality of one-shots to provide a plurality of alarm output signals.