US4677650A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Charge coupled semiconductor device with dynamic control
Assignee: US Philips Corp
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Filing: 1984-06-07
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Granted: 1987-06-30
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Expires: 2004-06-07
Abstract
Abstract In a CCD, especially in an image sensor device, the information density can be doubled by sequentially switching the electrodes between a clock signal and a reference signal. Clock signals and reference signals are obtained as output signals of a shift register controlled by a monophase or multiphase clock. The register is provided, for example, using C-MOS technology. Information at the input terminal of the first stage of the shift register in combination with clock pulse signals at the register clock, determine the output signals of the next stage of the shift register. Hence, these input signals determine the voltage variations at the electrodes connected to the outputs of the register stages.
Inventors
- 👤 Arnoldus J. J. Boudewijns
- 👤 Leonard J. M. Esser
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:35
CPC Classifications
H; H10; H10F; H10F39/00; H10F39/10; H10F39/12; H10F39/15; H10F39/153; G; G11; G11C; G11C19/00; G11C19/28; G11C19/282; G11C19/285; G11C27/00; H04; H04N; H04N25/00; H04N25/70; H04N25/71; H04N25/72; H04N25/745
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
134 words
A charge coupled semiconductor device comprising: a semiconductor body having a major surface, at least one charge transport channel being defined in the semiconductor body at the major surface; a system of clock electrodes on the major surface above the charge transport channel; and a shift register having a plurality of stages, each stage having an input and an output, the output of each stage being electrically connected to the input of the next succeeding stage; characterized in that: each clock electrode is directly electrically connected to an input or an output of a shift register stage or to an input/output connection of adjacent shift register stages; and at least one clock electrode forms the electrical connection between the output of one shift register stage and the input of the next shift register stage.
Claim 2
Dependent Claim
134 words
A charge coupled semiconductor device comprising: a semiconductor body having a major surface, at least one charge transport channel being defined in the semiconductor body at the major surface; a system of clock electrodes on the major surface above the charge transport channel; and a shift register having a plurality of stages, each stage having an input and an output, the output of each stage being electrically connected to the input of the next succeeding stage; characterized in that: each clock electrode is directly electrically connected to an input or an output of a shift register stage or to an input/output connection of adjacent shift register stages; and at least one clock electrode forms the electrical connection between the output of one shift register stage and the input of the next shift register stage.
Claim 3
Dependent Claim
18 words
A device as claimed in claim 1, characterized in that the shift register is a dynamic shift register.
Claim 4
Dependent Claim
35 words
A device as claimed in claim 2, characterized in that each stage of the shift register comprises: an inverter circuit having an input; and a switching transistor connected to the input of the inverter circuit.
Claim 5
Dependent Claim
18 words
A device as claimed in claim 3, characterized in that the inverter circuit comprises two complementary MOS transistors.
Claim 6
Dependent Claim
51 words
A device as claimed in claim 1, characterized in that the shift register comprises first and second subregisters, the first subregister being arranged on a first side of the charge transport channel, the second subregister being arranged on a second side of the charge transport channel, opposite to the first side.
Claim 7
Dependent Claim
193 words
A charge coupled semiconductor device comprising: a semiconductor body having a major surface, at least one charge transport channel being defined in the semiconductor body at the major surface; a system of clock electrodes on the major surface above the charge transport channel; and a shift register having a plurality of stages, each stage having an input and an output, the output of each stage being electrically connected to the input of the next succeeding stage; characterized in that: the shift register comprises first and second subregisters, the first subregister being arranged on a first side of the charge transport channel, the second subregister being arranged on a second side of the charge transport channel, opposite to the first side; each clock electrode is directly electrically connected to an input or an output of a shift register stage, or to an input/output connection of adjacent shift register stages; and at least one clock electrode forms the electrical connection between the output of one shift register stage on the first side of the charge transport channel and the input of the next shift register stage on the second side of the charge transport channel.
Claim 8
Dependent Claim
193 words
A charge coupled semiconductor device comprising: a semiconductor body having a major surface, at least one charge transport channel being defined in the semiconductor body at the major surface; a system of clock electrodes on the major surface above the charge transport channel; and a shift register having a plurality of stages, each stage having an input and an output, the output of each stage being electrically connected to the input of the next succeeding stage; characterized in that: the shift register comprises first and second subregisters, the first subregister being arranged on a first side of the charge transport channel, the second subregister being arranged on a second side of the charge transport channel, opposite to the first side; each clock electrode is directly electrically connected to an input or an output of a shift register stage, or to an input/output connection of adjacent shift register stages; and at least one clock electrode forms the electrical connection between the output of one shift register stage on the first side of the charge transport channel and the input of the next shift register stage on the second side of the charge transport channel.
Claim 9
Dependent Claim
20 words
A device as claimed in claim 6, characterized in that each subregister is arranged transverse to the charge transport channel.
References Cited (Backward Citations)
US3781574A
Cited
US3913077A
Cited
US4037119A
Cited
US3967254A
Cited
US4094009A
Cited
US4178614A
Cited
US4559550A
Cited
US4569067A
Cited
US4595845A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-06-29 | 1990-12-29 | 1991-06-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-06-29 | 1994-12-29 | 1995-06-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-06-29 | 1998-12-29 | 1999-06-30 | $7700.00 | Window Closed / Lapsed |