Charge transfer delay circuit for analog signals

Claim 1

A charge transfer delay circuit for delaying analog signals wherein there is provided a first longitudinal chain (K) of series-connected indentical stages operated in such a way that in a first clock phase, the even-numbered stages, switched by a first clock signal, contain an analog signal voltage value, while the odd-numbered stages, switched by a second clock signal, contain a neutral voltage value, whereas during the following clock phase, the odd-numbered stages contain an analog signal voltage value and the even-numbered stages contain a neutral voltage value comprising: a plurality of transversal chains (Q 1 , Q 2n , Q k-1 , Q k ) each comprising an identical number (n) of series-connected stages, each of said plurality of transversal chains connected to a different alternate stage of said first longitudinal chain; an n stage shift register for generating and applying n auxiliary clock signal (φ 3 ,1, φ 3 ,2, φ 3 ,n-1, φ 3 ,n), one to each of the n stages of said plurality of transversal chains, all stages in the transversal chains occupying a similar position in its respective chain being coupled to the same stage of said n-stage shift register, for activating the n stages of said first plurality of transversal chains, one at a time in turn; a second longitudinal chain (K') of series-arranged identical stages, alternate stages of which are coupled to a different one of said plurality of transversal chains; and means for applying a third clock signal to the even stages of said second longitudinal chain and a fourth clock signal to the odd numbered stages of said second longitudinal chain.