Patent US4677582A successfully refreshed from Google Patents.
US4677582A
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Operation processing apparatus
Assignee: Hitachi Ltd
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Filing: 1983-04-14
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Granted: 1987-06-30
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Expires: 2003-04-14
Abstract
Abstract An operation processing apparatus executes an instruction accompanied by addition/subtraction for one word and halfword operands at a high speed. An expander expands the sign of a second operand in its upper halfword bits to produce an expanded second operand having the same length as that of a first operand. An arithmetic unit operates the first operand and the expanded second operand.
Inventors
- 👤 Motonobu Nagafuji
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:07
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/3001; G06F9/30014
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
219 words
An operation processing apparatus comprising: first register means for holding a first operand having a sign bit; second register means for holding a second operand having a sign bit, the length of said second operand being smaller than that of the first operand; expanding means connected to the second register means to produce an expanded second operand having additional bits based on the sign bit of said second operand in the upper bits thereof and having said second operand in the lower bits thereof so that the expanded second operand has the same length as that of said first operand, said expanding means including first gate means for outputting the second operand in said second register as the lower bits of said expanded second operand, and second gate means for outputting additional bits based on the sign bit of said second operand to form the upper bits of said expanded second operand, said second gate means including a plurality of gates each corresponding to a respective one of the upper bits of said expanded second operand, said sign bit being applied in common to an input of each of said plurality of gates; and arithmetic means for executing an arithmetic operation on said first operand from said first register means and said expanded second operand from said expanding means.
Claim 2
Dependent Claim
219 words
An operation processing apparatus comprising: first register means for holding a first operand having a sign bit; second register means for holding a second operand having a sign bit, the length of said second operand being smaller than that of the first operand; expanding means connected to the second register means to produce an expanded second operand having additional bits based on the sign bit of said second operand in the upper bits thereof and having said second operand in the lower bits thereof so that the expanded second operand has the same length as that of said first operand, said expanding means including first gate means for outputting the second operand in said second register as the lower bits of said expanded second operand, and second gate means for outputting additional bits based on the sign bit of said second operand to form the upper bits of said expanded second operand, said second gate means including a plurality of gates each corresponding to a respective one of the upper bits of said expanded second operand, said sign bit being applied in common to an input of each of said plurality of gates; and arithmetic means for executing an arithmetic operation on said first operand from said first register means and said expanded second operand from said expanding means.
Claim 3
Dependent Claim
25 words
An operation processing apparatus according to claim 1 wherein said first operand comprises a one word operand and said second operand comprises a half-word operand.
Claim 4
Dependent Claim
48 words
An operation processing apparatus according to claim 2 wherein said first gate means operates to pass said second operand through as it is, and said second gate means passes the sign bit of said second operand in each of the upper halfword bits of the expanded second operand.
Claim 5
Dependent Claim
16 words
An operation processing apparatus according to claim 3 wherein said arithmetic means executes a addition operation.
Claim 6
Dependent Claim
68 words
An operation processing apparatus according to claim 1 wherein said expanding means includes control means responsive to execution of a subtraction or compare operation for controlling said first gate means to pass a complement of said second operand and said second gate means to pass the inverted signal bit of said second operand for applying an initial carry bit to the lowest bit position of said arithmetic means.
Claim 7
Dependent Claim
25 words
An operation processing apparatus according to claim 5 wherein said first operand comprses a one word operand and asid second operand comprises a halfword operand.
Claim 8
Dependent Claim
50 words
An operation processing apparatus according to claim 6 wherein said control means is responsive to execution of a subtraction or compare operation for controlling said second gate means to pass the inverted sign bit of said second operand in each of the upper halfword bits of the expanded second operand.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-06-29 | 1990-12-29 | 1991-06-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-06-29 | 1994-12-29 | 1995-06-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-06-29 | 1998-12-29 | 1999-06-30 | $7700.00 | Window Closed / Lapsed |