Patent US4677499A successfully refreshed from Google Patents.
US4677499A
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US
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Digital time base corrector
Assignee: Sony Corp
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Filing: 1985-04-10
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Granted: 1987-06-30
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Expires: 2005-04-10
Abstract
Abstract There is provided a digital time base corrector in which a digital input signal of one block consisting of a continuous data time sequence is converted to a digital signal including data lack intervals or vice versa by a variable delay circuit. A signal selecting circuit is divided into N first unit selecting circuits and a second unit selecting circuit. M of the output signals of a shift register are inputted to the first unit selecting circuits, by which one of them is selected. The outputs of the N first unit selecting circuits are supplied to the second unit selecting circuit, by which one of them is selected. A pipeline process is performed by inserting a delay circuit to delay the signal for the time of one clock period into the input/output line of the second unit selecting circuit. Further, the selecting signal can be made variable for every one clock and a delay circuit is inserted on the output side of a selecting signal forming circuit. With this corrector, the influence of the gate delay of the selectors can be reduced and the high speed data process can be performed.
Inventors
- 👤 Norihisa Shirota
- 👤 Takao Yamazaki
- 👤 Seiichiro Iwase
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 10:24
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/131; G; G11; G11B; G11B20/00; G11B20/10; G11B20/18; H04; H04N; H04N5/00; H04N5/76; H04N5/91; H04N5/93; H04N5/95; H03K2005/00013; H03K2005/0015; H03K2005/00234; H03K2005/00241
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
249 words
A digital time base corrector for correcting the time base of a serial input digital information signal with a predetermined clock frequency comprising: (A) a delay circuit supplied with said serial input digital information signal and for generating a plurality of delayed outputs therefrom, each having different respective time delays; (B) a first group of selecting circuits, each of which is supplied with M of said delayed outputs as inputs thereof and for selecting one of said inputs, wherein M is a positive integer; (C) a plurality of unit delay circuits, each of said delay circuits being connected to the output of a respective one of said selecting circuits and for delaying the output signal of said selecting circuit for one clock period; (D) a second selecting circuit supplied with the outputs of said unit delay circuits and for selecting one of said outputs; (E) a selecting signal generating circuit supplied with a digital selecting signal that determines an extent of time base correction to be applied to said input digital signal and which is varied at every clock period for generating first and second selecting signals; and (F) first and second register means connected respectively to said first and second selecting signals of said selecting signal generator and for delaying said first and second selecting signals, respectively, the output of said first register means being supplied to said first group of selecting circuits and the output of said second register means being supplied to said second selecting circuit.
Claim 2
Dependent Claim
249 words
A digital time base corrector for correcting the time base of a serial input digital information signal with a predetermined clock frequency comprising: (A) a delay circuit supplied with said serial input digital information signal and for generating a plurality of delayed outputs therefrom, each having different respective time delays; (B) a first group of selecting circuits, each of which is supplied with M of said delayed outputs as inputs thereof and for selecting one of said inputs, wherein M is a positive integer; (C) a plurality of unit delay circuits, each of said delay circuits being connected to the output of a respective one of said selecting circuits and for delaying the output signal of said selecting circuit for one clock period; (D) a second selecting circuit supplied with the outputs of said unit delay circuits and for selecting one of said outputs; (E) a selecting signal generating circuit supplied with a digital selecting signal that determines an extent of time base correction to be applied to said input digital signal and which is varied at every clock period for generating first and second selecting signals; and (F) first and second register means connected respectively to said first and second selecting signals of said selecting signal generator and for delaying said first and second selecting signals, respectively, the output of said first register means being supplied to said first group of selecting circuits and the output of said second register means being supplied to said second selecting circuit.
Claim 3
Dependent Claim
37 words
A digital time base corrector according to claim 1, wherein said first register means delays said first selecting signal for one clock period and said second register means delays said second selecting signal for two clock periods.
Claim 4
Dependent Claim
35 words
A digital time base corrector according to claim 2, wherein said delay circuit includes a plurality of registers and each of said plurality of outputs is obtained at the output of each of said registers.
Claim 5
Dependent Claim
56 words
A digital time base corrector according to claim 1, wherein said selecting signal generating circuit includes first and second decoders for generating said first and second selecting signals, respectively, lower bits of said digital selecting signal being supplied to said first decoder and higher bits of said digital selecting signal being supplied to said second decoder.
Claim 6
Dependent Claim
39 words
A digital time base corrector according to claim 1, wherein said input digital signal is a serial data sequence in one block and the output of said second selecting circuit has a data blanking period in said one block.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-06-29 | 1990-12-29 | 1991-06-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-06-29 | 1994-12-29 | 1995-06-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-06-29 | 1998-12-29 | 1999-06-30 | $7700.00 | Window Closed / Lapsed |