US3851100A
Expired / Lapsed
US
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Time-base error correction system
Assignee: Ampex Corp
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Filing: 1973-06-14
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Granted: 1974-11-26
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Expires: 1993-06-14
Abstract
Abstract A time-base error correction system for a video signal employing a plurality of serially connected delay lines. Circuit means are conditioned to detect the closest timing match between a reference synchronizing signal and the video signal as it appears at various points along the delay path and to connect the appropriate delay line point or junction to an output at which the correctly delayed video signal appears. Featured circuitry provides for eliminating the erroneous leading edge of a video synchronizing pulse distorted by changes in the selected delay point and for compensating for variations in d.c. offset of the video signal introduced by differential delay line path effects.
Inventors
- 👤 W Herzog
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:00
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/76; H04N5/91; H04N5/92; H04N5/93; H04N5/95
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
213 words
In a time-base error correction system having a plurality of serially connected delay lines defining taps therebetween and disposed to receive a video signal therethrough, detection means comparing a reference timing signal with a synchronizing waveform of the video signal as it appears at the taps of said delay lines, and switching means connecting a selected one of said taps to a video output in response to the detection means, the improvement in said detection means comprising: a separate electrical flip-flop means associated with each of said taps and each having an output connected to and operating said switching means to connect the associated tap to said video output, a separate sync pulse detector connected to each tap for sensing the occurrence of said video signal waveform therewith, a permit selection pulse generator receiving said reference signal and generating a permit selection pulse in response thereto, gating means connecting each said sync pulse detector to an input of an associated flip-flop means for switching the state thereof, said gating means having a control input connected to said permit selection pulse generator for enabling said gating means in response thereto, whereby the input of said flip-flop means is responsive to an associated detection only when said gating means is enabled by a permit selection.
Claim 2
Dependent Claim
213 words
In a time-base error correction system having a plurality of serially connected delay lines defining taps therebetween and disposed to receive a video signal therethrough, detection means comparing a reference timing signal with a synchronizing waveform of the video signal as it appears at the taps of said delay lines, and switching means connecting a selected one of said taps to a video output in response to the detection means, the improvement in said detection means comprising: a separate electrical flip-flop means associated with each of said taps and each having an output connected to and operating said switching means to connect the associated tap to said video output, a separate sync pulse detector connected to each tap for sensing the occurrence of said video signal waveform therewith, a permit selection pulse generator receiving said reference signal and generating a permit selection pulse in response thereto, gating means connecting each said sync pulse detector to an input of an associated flip-flop means for switching the state thereof, said gating means having a control input connected to said permit selection pulse generator for enabling said gating means in response thereto, whereby the input of said flip-flop means is responsive to an associated detection only when said gating means is enabled by a permit selection.
Claim 3
Dependent Claim
213 words
In a time-base error correction system having a plurality of serially connected delay lines defining taps therebetween and disposed to receive a video signal therethrough, detection means comparing a reference timing signal with a synchronizing waveform of the video signal as it appears at the taps of said delay lines, and switching means connecting a selected one of said taps to a video output in response to the detection means, the improvement in said detection means comprising: a separate electrical flip-flop means associated with each of said taps and each having an output connected to and operating said switching means to connect the associated tap to said video output, a separate sync pulse detector connected to each tap for sensing the occurrence of said video signal waveform therewith, a permit selection pulse generator receiving said reference signal and generating a permit selection pulse in response thereto, gating means connecting each said sync pulse detector to an input of an associated flip-flop means for switching the state thereof, said gating means having a control input connected to said permit selection pulse generator for enabling said gating means in response thereto, whereby the input of said flip-flop means is responsive to an associated detection only when said gating means is enabled by a permit selection.
Claim 4
Dependent Claim
213 words
In a time-base error correction system having a plurality of serially connected delay lines defining taps therebetween and disposed to receive a video signal therethrough, detection means comparing a reference timing signal with a synchronizing waveform of the video signal as it appears at the taps of said delay lines, and switching means connecting a selected one of said taps to a video output in response to the detection means, the improvement in said detection means comprising: a separate electrical flip-flop means associated with each of said taps and each having an output connected to and operating said switching means to connect the associated tap to said video output, a separate sync pulse detector connected to each tap for sensing the occurrence of said video signal waveform therewith, a permit selection pulse generator receiving said reference signal and generating a permit selection pulse in response thereto, gating means connecting each said sync pulse detector to an input of an associated flip-flop means for switching the state thereof, said gating means having a control input connected to said permit selection pulse generator for enabling said gating means in response thereto, whereby the input of said flip-flop means is responsive to an associated detection only when said gating means is enabled by a permit selection.
Claim 5
Dependent Claim
113 words
In the system of claim 1, the improvement in said detection means further comprising, an inhibit select pulse generator, an OR logic gate having separate inputs individually connected to the outputs of said flip-flops and having an output connected to and operating said inhibit pulse generator, said gating means connected and responsive to an output of said inhibit circuit pulse generator for disabling the response of each of said flip-flops to said sync pulse detectors, whereby said inhibit pulse generator is actuated once one of said flip-flops is switched and the inhibit pulse generated in response thereto operates said gating means to disable further response of the flip-flops to said sync pulse detectors.
Claim 6
Dependent Claim
196 words
In a time-base error correction system having a plurality of serially connected delay lines defining taps therebetween and disposed to receive a video signal therethrough, detection means comparing a reference timing signal with a synchronizing waveform of the video signal as it appears at the taps between said delay lines, and switching means connecting a selected one of said taps to a video output in response to the detection of the first occurring video synchronizing waveform at one of said junctions following the reference timing signal, the combination with said delay lines, detection means and switching means comprising; video signal gating means interposed between said switching means and said video output, control circuit means connected to an input to said delay lines and to said detection means and being responsive to a leading edge of said video waveform at an input to said delay lines to dispose said video gating means in a gate-off condition and said control circuit means being responsive to detection of said first occurring video waveform following the reference signal to dispose said video gating means in a gate-on condition, whereby a stretched leading edge of the video synchronizing waveform is cancelled.
Claim 7
Dependent Claim
196 words
In a time-base error correction system having a plurality of serially connected delay lines defining taps therebetween and disposed to receive a video signal therethrough, detection means comparing a reference timing signal with a synchronizing waveform of the video signal as it appears at the taps between said delay lines, and switching means connecting a selected one of said taps to a video output in response to the detection of the first occurring video synchronizing waveform at one of said junctions following the reference timing signal, the combination with said delay lines, detection means and switching means comprising; video signal gating means interposed between said switching means and said video output, control circuit means connected to an input to said delay lines and to said detection means and being responsive to a leading edge of said video waveform at an input to said delay lines to dispose said video gating means in a gate-off condition and said control circuit means being responsive to detection of said first occurring video waveform following the reference signal to dispose said video gating means in a gate-on condition, whereby a stretched leading edge of the video synchronizing waveform is cancelled.
Claim 8
Dependent Claim
99 words
The combination as defined in claim 3 further comprising; OR logic circuit means connected to said control circuit means having an input responsive to said detected first occurring video waveform following the reference signal and another input responsive to the video waveform appearing at an output tap of the last serially connected delay line such that said control circuit means operates to dispose said video gating means in its gateon condition in response to either of the inputs to said OR lOgic means, whereby said gating means is released from its gate-off condition in the absence of said detection.
Claim 9
Dependent Claim
64 words
The combination of claim 5 in which said switching means includes a separate switch control and switch for each delay line tap, and said AND logic means comprises an AND gate having inputs connected to each of said separate switch controls and said circuit means having an output connected to and for operating one of said switches associated with one of said switch controls.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-11-25 | 1978-05-27 | 1978-11-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-11-25 | 1982-05-27 | 1982-11-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-11-25 | 1986-05-27 | 1986-11-26 | $7700.00 | Window Closed / Lapsed |