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US4673830A Expired / Lapsed US ⏱️ 0.0 years remaining

Biasing network for multifunction bipolar integrated system

Assignee: Telecom Italia SpA
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Filing: 1984-05-11
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Granted: 1987-06-16
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Expires: 2004-05-11
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Abstract

Abstract A network for supplying identical biasing voltages and programmable direct currents to a plurality of mutually similar transceivers, connected across respective transmission lines, is integrated with the associated transceivers in a common semiconductor body and comprises a generator of fixed reference voltage determined by the band gap of the semiconductor. The reference voltage is applied in parallel to the bases of several NPN transistors emitting the same biasing voltage as a result thereof. This reference voltage also drives an NPN pilot transistor lying in series with an external resistor through which it draws a small programmed current. Through two cascaded amplification stages formed by NPN transistors operating in the ECL mode, with the second stage designed as a multiple-output current mirror, the programmed current is stepped up to provide the several direct currents required by the associated transceivers.

Inventors

  • 👤 Valerio Giorgetta
  • 👤 Vanni Poletta
  • 👤 Mario Sartori
  • 👤 Marco Siligoni

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 20:02
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/22

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 216 words
An integrated circuit comprising: a unitary semiconductor body; a plurality of substantially identical circuit elements integrated in said body and connected to be energized with biasing voltages, fixed currents and programmable currents; a reference-voltage generator integrated in said body for generating a stabilized reference voltage; first transistors integrated in said body and connected to said reference-voltage generator and controlled by said stabilized reference voltage for delivering respective biasing voltages of identical magnitudes to control inputs of all of said circuit elements, said first transistors effectively maintaining said control inputs decoupled from one another in spite of the application to said control inputs of identical bias voltages; second transistors integrated in said body and connected to said reference-voltage generator and controlled by said stabilized reference voltage for producing a small current; and a two-stage amplifier comprised of third transistors integrated in said body and connected to said second transistors and receiving said small current and amplifying same, said third transistors including respective output transistors programmable by respective resistors in circuit therewith and applying respective programmable currents to drive inputs of said circuit elements, said output transistors effectively maintaining said drive inputs decoupled from one another in spite of the application to said drive inputs of said programmable currents derived from a common first stage of said amplifier.
Claim 2
Dependent Claim 216 words
An integrated circuit comprising: a unitary semiconductor body; a plurality of substantially identical circuit elements integrated in said body and connected to be energized with biasing voltages, fixed currents and programmable currents; a reference-voltage generator integrated in said body for generating a stabilized reference voltage; first transistors integrated in said body and connected to said reference-voltage generator and controlled by said stabilized reference voltage for delivering respective biasing voltages of identical magnitudes to control inputs of all of said circuit elements, said first transistors effectively maintaining said control inputs decoupled from one another in spite of the application to said control inputs of identical bias voltages; second transistors integrated in said body and connected to said reference-voltage generator and controlled by said stabilized reference voltage for producing a small current; and a two-stage amplifier comprised of third transistors integrated in said body and connected to said second transistors and receiving said small current and amplifying same, said third transistors including respective output transistors programmable by respective resistors in circuit therewith and applying respective programmable currents to drive inputs of said circuit elements, said output transistors effectively maintaining said drive inputs decoupled from one another in spite of the application to said drive inputs of said programmable currents derived from a common first stage of said amplifier.
Claim 3
Dependent Claim 280 words
In combination, a plurality of substantially identical circuit components including transceivers connected across respective transmission lines and associated with a common biasing network, all integrated in a unitary semiconductor body, said biasing network comprising: a source of direct current having two supply leads of a positive and a negative relative polarity, respectively; a voltage generator including transistor means connected across said supply leads for producing a fixed reference voltage determined by a band gap of the semiconductor of said body, said voltage generator comprising a set of transistors interconnected as a Widlam mirror and provided with a starting circuit; a plurality of NPN first output transistors with collectors connected to one of said supply leads, bases connected in parallel to said generator for receiving said reference voltage therefrom, and emitters connected to first terminals of respective associated circuit components for energizing same with an identical biasing voltage controlled by the refernce voltage supplied to said bases; a pilot transistor connected across said supply leads in series with an external resistor for drawing a small programmed current under the control of said reference voltage applied to a base thereof by said voltage generator; amplifier means connected to said pilot transistor for stepping up said programmed current, said amplifier means including a final stage a plurality of second NPN output transistors inserted in series with respective emitter resistors between the other of said supply leads and second terminals of respective associated circuit components for energizing same with respective direct currents programmable by the magnitudes of said emitter resistors; and a decoupling circuit inserted between said pilot transistor and said amplifier means, said decoupling circuit comprising a PNP current mirror with base-current feedback.
Claim 4
Dependent Claim 280 words
In combination, a plurality of substantially identical circuit components including transceivers connected across respective transmission lines and associated with a common biasing network, all integrated in a unitary semiconductor body, said biasing network comprising: a source of direct current having two supply leads of a positive and a negative relative polarity, respectively; a voltage generator including transistor means connected across said supply leads for producing a fixed reference voltage determined by a band gap of the semiconductor of said body, said voltage generator comprising a set of transistors interconnected as a Widlam mirror and provided with a starting circuit; a plurality of NPN first output transistors with collectors connected to one of said supply leads, bases connected in parallel to said generator for receiving said reference voltage therefrom, and emitters connected to first terminals of respective associated circuit components for energizing same with an identical biasing voltage controlled by the refernce voltage supplied to said bases; a pilot transistor connected across said supply leads in series with an external resistor for drawing a small programmed current under the control of said reference voltage applied to a base thereof by said voltage generator; amplifier means connected to said pilot transistor for stepping up said programmed current, said amplifier means including a final stage a plurality of second NPN output transistors inserted in series with respective emitter resistors between the other of said supply leads and second terminals of respective associated circuit components for energizing same with respective direct currents programmable by the magnitudes of said emitter resistors; and a decoupling circuit inserted between said pilot transistor and said amplifier means, said decoupling circuit comprising a PNP current mirror with base-current feedback.
Claim 5
Dependent Claim 27 words
The combination defined in claim 1 wherein said amplifier means includes an input stage comprising a floating NPN current mirror in cascade with said PNP current mirror.
Claim 6
Dependent Claim 55 words
The combination defined in claim 1 wherein each of said transceivers has an input terminal connected to a source of incoming binary signals and a further terminal connected to said biasing network for receiving therefrom a fixed potential derived from said reference voltage, said fixed potential lying between the binary levels of said incoming signals.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1990-06-15 1990-12-15 1991-06-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1994-06-15 1994-12-15 1995-06-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1998-06-15 1998-12-15 1999-06-16 $7700.00 Window Closed / Lapsed

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