Built in self test input generator for programmable logic arrays

Claim 2

A built in self test input generator (BISTIG) for a programmable logic array (PLA), wherein the PLA comprises a first level array adapted to receive N input signals in N input lines and to provide M product terms on M product term lines, and a second level array adapted to receive the M product terms on the M product term lines and to provide P output signals on P output lines, wherein N, M, and P are integers greater than one, the BISTIG comprising: a test vector generator comprising: a test signal input line originating from a test computer; a log 2 (N) sequence generator for providing log 2 (N) outputs along a plurality of lines to a one-of-N decoder which, in response to the outputs from the log 2 (N) sequence generator, drives a set of N test input lines which the test vector generator couples to the N input lines of the PLA; wherein the test vector generator responds to a test signal on the test signal input line, by providing N test vectors on the N input lines of the first level array of the PLA; and a product term control comprising: a test signal input line originating from a test computer; a log 2 (M) sequence generator for providing log 2 (M) outputs along a plurality of lines to a one-of-M decoder which, in response to the outputs from the log 2 (M) sequence generator, selectively enables the M product term lines of the second PLA individually; wherein the product term control responds to a test signal on the test signal input line.

Claim 3

The BISTIG of claim 1 wherein the test vector generator further comprises means for selectively complementing the test vectors consisting of multiplexing means accepting input from the N test lines of the one-of-N decoder and providing output to the N input lines of the first level array of the PLA, wherein the multiplexing means is for selecting between the true or complement of the generated tests and for choosing between normal and test inputs.

Claim 4

The BISTIG of claim 2 wherein the multiplexing means selects between the true or the complement of said test vectors in response to a T signal on a T signal input line to the multiplexing means.

Claim 5

The BISTIG of claim 3 wherein the BISTIG includes a trigger flip-flop for providing the T signal to the multiplexing means on the T signal input line, for resetting the sequence generator of the test vector generator and for sequencing the sequence generator of the product term control in response to a clock of the PLA and in response to a last test vector generated out of the one-of-N decoder.

Claim 6

The BISTIG of claim 1 wherein the log 2 (N) and log 2 (M) sequence generators are linear feedback shift registers.

Claim 7

A built in self test input generator (BISTIG) for a programmable logic array (PLA), wherein the PLA comprises a first level array adapted to receive 2N input signals on N input lines and to provide M product terms on M product term lines, and a second level array adapted to receive the M product terms on the M product term lines and to provide P output signals on P output lines, wherein N, M and P are integers greater than one, the BISTIG comprising: a test vector generator comprising: a test signal input line originating from a test computer; a log 2 (N) linear feedback shift register for providing log 2 (N) outputs along a plurality of lines to a one-of-N decoder which, in response to the outputs from the log 2 (N) sequence generator, drives a set of N test input lines which the test vector generator couples to the N input lines of the PLA; and multiplexing means accepting input from the N test lines of the one-of-N decoder and providing output to the N input lines of the first level array of the PLA, wherein the multiplexing means is for selecting between the true or complement of the generated tests and for choosing between normal and test inputs; wherein the test vector generator responds to a test signal on the test signal input line, by providing N test vectors on the N input lines of the first level array of the PLA; and a product term control comprising: a test signal input line originating from a test computer; a log 2 (M) linear feedback shift register for providing log 2 (M) outputs along a plurality of lines to a one-of-M decoder which, in response to the outputs from the log 2 (M) sequence generator, selectively enables the M product term lines of the second PLA individually; wherein the product term control responds to the test signal on the test signal input line.

Claim 8

A built in self test input generator (BISTIG) for a programmable logic array (PLA), wherein the PLA comprises a first level array adapted to receive 2N input signals on N input lines and to provide M product terms on M product term lines, and a second level array adapted to receive the M product terms on the M product term lines and to provide P output signals on P output lines, wherein N, M and P are integers greater than one, the BISTIG comprising: a test vector generator comprising: a test signal input line originating from a test computer; a log 2 (N) linear feedback shift register for providing log 2 (N) outputs along a plurality of lines to a one-of-N decoder which, in response to the outputs from the log 2 (N) sequence generator, drives a set of N test input lines which the test vector generator couples to the N input lines of the PLA; and multiplexing means accepting input from the N test lines of the one-of-N decoder and providing output to the N input lines of the first level array of the PLA, wherein the multiplexing means is for selecting between the true or complement of the generated tests and for choosing between normal and test inputs; wherein the test vector generator responds to a test signal on the test signal input line, by providing N test vectors on the N input lines of the first level array of the PLA; and a product term control comprising: a test signal input line originating from a test computer; a log 2 (M) linear feedback shift register for providing log 2 (M) outputs along a plurality of lines to a one-of-M decoder which, in response to the outputs from the log 2 (M) sequence generator, selectively enables the M product term lines of the second PLA individually; wherein the product term control responds to the test signal on the test signal input line.