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US4672609A
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Memory system with operation error detection
Assignee: Tandem Computers Inc
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Filing: 1986-03-28
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Granted: 1987-06-09
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Expires: 2006-03-28
Abstract
Abstract A memory system for a computer detects data errors, address errors and operation errors to increase the reliability of data stored in the memory system. Address errors are detected by encoding address parity information into the data check field of each memory location. A signal is generated in each memory module indicating the status of operations of that memory module and is transmitted to the processor subsystem of the computer for comparison with a signal indicating the status of operations of the processor subsystem to insure that all memory modules and the memory control in the processor are receiving the same commands.
Inventors
- 👤 Richard A. Humphrey
- 👤 Steven D. Fisher
- 👤 Steven W. Wierenga
- 👤 Jon Sjostedt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 05:25
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1012; G06F11/1016; G06F11/0703; G06F11/0751; G11; G11C; G11C29/00; G11C29/02
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
93 words
A method of monitoring operation of a memory system that is operable in response to control signals received from a processing unit, the method comprising the steps of: producing first and second digital state signals, each being respectively associated with the processing unit and the memory system, and each being indicative of the (1) control signals produced by the processing unit and received by the memory system and (2) prior produced digital state signals; and comparing the first and second digital state signals to produce therefrom an error signal indicative of improper operation.
Claim 2
Independent Claim
93 words
A method of monitoring operation of a memory system that is operable in response to control signals received from a processing unit, the method comprising the steps of: producing first and second digital state signals, each being respectively associated with the processing unit and the memory system, and each being indicative of the (1) control signals produced by the processing unit and received by the memory system and (2) prior produced digital state signals; and comparing the first and second digital state signals to produce therefrom an error signal indicative of improper operation.
Claim 3
Dependent Claim
167 words
In a memory system for storing and retrieving data signals in response to command signals generated by a command means for directing operation of the memory system apparatus for detecting improper memory operation, the apparatus comprising, first state machine means associated with the memory system and coupled to receive the command signals for sequentially assuming a plurality of digital states, second state machine means associated with the command means and coupled to receive the command signals for sequentially assuming a plurality of predetermined digital states, each of the assumed digital states assumed by the first and second state machine means being identical to one another when proper memory system operation occurs, and each of the assumed digital states being determined by the operation dictated by the command signals during an immediately prior assumed digital state and said prior assumed digital state, and circuit means coupled to the first and second state machines means to compare the assumed digital states of each for determining improper memory operation therefrom.
Claim 4
Dependent Claim
167 words
In a memory system for storing and retrieving data signals in response to command signals generated by a command means for directing operation of the memory system apparatus for detecting improper memory operation, the apparatus comprising, first state machine means associated with the memory system and coupled to receive the command signals for sequentially assuming a plurality of digital states, second state machine means associated with the command means and coupled to receive the command signals for sequentially assuming a plurality of predetermined digital states, each of the assumed digital states assumed by the first and second state machine means being identical to one another when proper memory system operation occurs, and each of the assumed digital states being determined by the operation dictated by the command signals during an immediately prior assumed digital state and said prior assumed digital state, and circuit means coupled to the first and second state machines means to compare the assumed digital states of each for determining improper memory operation therefrom.
Claim 5
Dependent Claim
141 words
In a memory system for storing data in response to command signals issued from a circuit means that controls memory system operation, memory operation error detection apparatus for detecting improper memory operation, the apparatus comprising: first and second operation state machine means respectively associated with said memory system and said circuit means for sequentially assuming individual ones of a plurality of predetermined digital states in response to the command signals, each assumed digital state being determined, at least in part, by assertion of a command signal during an immediately prior assumed digital state, each of the first and second operation state machine means including means for providing an operation state signal indicative of a current assumed digital state, and comparing means coupled to receive the operation state signals and operable to produce an operation check error signal, indicating improper memory operation.
Claim 6
Dependent Claim
141 words
In a memory system for storing data in response to command signals issued from a circuit means that controls memory system operation, memory operation error detection apparatus for detecting improper memory operation, the apparatus comprising: first and second operation state machine means respectively associated with said memory system and said circuit means for sequentially assuming individual ones of a plurality of predetermined digital states in response to the command signals, each assumed digital state being determined, at least in part, by assertion of a command signal during an immediately prior assumed digital state, each of the first and second operation state machine means including means for providing an operation state signal indicative of a current assumed digital state, and comparing means coupled to receive the operation state signals and operable to produce an operation check error signal, indicating improper memory operation.
Claim 7
Dependent Claim
19 words
The apparatus of claim 3 wherein, the command signals correspond to a number of types of memory system operations.
Claim 8
Dependent Claim
31 words
The apparatus of claim 3, wherein the first and second state machine means each include logic function means coupled to receive the command signals for producing therefrom the current digital state.
Claim 9
Dependent Claim
32 words
The apparatus of claim 5, wherein the first and second state machine means each include state register means for receiving and holding the current digital state produced by the logic function means.
Claim 10
Dependent Claim
34 words
The apparatus of claim 6, wherein the logic function means is coupled to the state register means for receiving the prior-assumed digital state to produce, together with the command signals, the current digital state.
Claim 11
Dependent Claim
30 words
The apparatus of claim 5, wherein the logic function means includes means for receiving the prior-assumed digital state for providing, together with the received command signals, the current digital state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-06-08 | 1990-12-08 | 1991-06-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-06-08 | 1994-12-08 | 1995-06-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-06-08 | 1998-12-08 | 1999-06-09 | $7700.00 | Window Closed / Lapsed |