Inverter control circuit

Claim 1

An inverter control circuit comprising: (a) a central processing unit supplied with an operating command for an induction motor; (b) a storage device supplied with a voltage command signal from said central processing unit and stored therein with voltage patterns forming the basis of three-phase a.c. control signals and further stored therein in a different region from that for said patterns with voltage patterns dedicated for stopping to be used for stopping the induction motor; (c) a rate multiplier supplied with a frequency command signal from said central processing unit for outputting a frequency signal proportional to the frequency command signal; (d) a counter supplied with a frequency signal from said rate multiplier as the clock therefor for accessing an address of said storage device with its count signal; (e) a first data selector supplied with a frequency signal frequency-divided by said counter as the clock therefor for combining voltage patterns selected from said storage device by the voltage command signal; (f) second data selectors supplied with a frequency signal frequency-divided by said counter as the clock therefor for forming a three-phase a.c. control signal; and (g) a latch circuit disposed between said counter and address input to said second data selectors and supplied with a control signal from said central processing unit and an output signal from said counter as the clock therefor.