Waveform synthesizer and motor controller

Claim 2

A motor controller for selectively controlling an AC motor by providing a controlled power waveform thereto of selected wave shape and frequency, said motor controller comprising: a waveform memory means divided into p addressable pages representing p available wave shapes with each page divided into s addressable segments, the segments of each page having binary switch control information stored therein, the pages and the segments of each page addressable through a memory address port to provide the so-addressed switch control information to switch control data lines; selectively gatable switch means connected between a DC power source means to at least one output power node for connection to the motor to be controlled and connected to said switch control data lines; stored-program control means connected to said waveform memory for (a) addressing a selected one of the pages available in the waveform memory, and (b) sequentially addressing the segments of the addressed page at a selected sequential address rate to thereby cause the gatable switch means to switch DC power to the output node to synthesize a waveform of selected waveform and wave shape in accordance with the stored binary switch control information of the addressed page; said stored program control means including a stored-program-controlled processor means having an address output port connected to said memory address port for providing an addressing rate select signal, and a segment addressing means connected to said memory address port for sequentially addressing the segments of an addressed page at a selected addressing rate and connected to said address rate control port so as to provide a selected addressing rate in response to an addressing rate select signal provided from said processor means; and wherein said segment addressing means comprising a presettable frequency divider connected to a source of input pulses with the frequency divide rate set by said processor through said segment address rate select port, said presettable frequency divider connected and providing frequency divided input pulses to a segment address counter connected to said memory address port.

Claim 3

A motor controller for selectively controlling a poly-phase AC motor having at least two power phases by providing a controlled poly-phase power waveform thereto of selected wave shape and frequency, said motor controller comprising: a waveform memory means divided into p addressable pages representing p available wave shapes with each page divided into s addressable segments, the segments of each page having binary switch control information stored therein, the pages and the segments of each page addressable through a memory address port to provide the so-addressed switch control information to switch control data lines; selectively gatable switch means connected between a DC power source means to at least two output power nodes for connection to the motor to be controlled and connected to said switch control data lines; stored-program control means connected to said waveform memory for (a) addressing a selected one of the pages available in the waveform memory, and (b) sequentially addressing the segments of the addressed page at a selected sequential address rate to thereby cause the gatable switches to switch DC power to the output node to synthesize a waveform of selected waveform and wave shape in accordance with the stored binary switch control information of the addressed page; said stored program control means including a stored-program-controlled processor means having an address output port connected to said memory address port for providing a page select address and having an address rate control port for providing an addressing rate select signal, and a segment addressing means connected to said memory address port for sequentially addressing the segments of an addressed page at a selected addressing rate and connected to said address rate control port so as to provide a selected addressing rate in response to an addressing rate select signal provided from said processor means; and wherein said segment addressing means comprising a presettable frequency divider connected to a source of input pulses with the frequency divide rate set by said processor through said segment address rate select port, said presettable frequency divider connected and providing frequency divided input pulses to a segment address counter connected to said memory address port.

Claim 4

A motor controller for selectively controlling a poly-phase AC motor having at least two power phases by providing a controlled poly-phase power waveform thereto of selected wave shape and frequency, said motor controller comprising: a waveform memory means divided into p addressable pages representing p available wave shapes with each page divided into s addressable segments, the segments of each page having binary switch control information stored therein, the pages and the segments of each page addressable through a memory address port to provide the so-addressed switch control information to switch control data lines; selectively gatable switch means connected between a DC power source means to at least two output power nodes for connection to the motor to be controlled and connected to said switch control data lines; stored-program control means connected to said waveform memory for (a) addressing a selected one of the pages available in the waveform memory, and (b) sequentially addressing the segments of the addressed page at a selected sequential address rate to thereby cause the gatable switches to switch DC power to the output node to synthesize a waveform of selected waveform and wave shape in accordance with the stored binary switch control information of the addressed page; said stored program control means including a stored-program-controlled processor means having an address output port connected to said memory address port for providing a page select address and having an address rate control port for providing an addressing rate select signal, and a segment addressing means connected to said memory address port for sequentially addressing the segments of an addressed page at a selected addressing rate and connected to said address rate control port so as to provide a selected addressing rate in response to an addressing rate select signal provided from said processor means; and wherein said segment addressing means comprising a presettable frequency divider connected to a source of input pulses with the frequency divide rate set by said processor through said segment address rate select port, said presettable frequency divider connected and providing frequency divided input pulses to a segment address counter connected to said memory address port.

Claim 5

A motor controlled for selectively controlling a poly-phase induction motor having at least two power phases by providing a controlled power waveform thereto of selected wave shape and frequency, said motor controller comprising: a waveform memory means divided into p addressable pages representing p available wave shapes with each page divided into s addressable segments, the segments of each page having binary switch control information stored therein, the pages and the segments of each page addressable through a memory address port to provide the so-addressed switch control information to switch control data lines; selectively gatable switch means connected between DC power source means to at least two output power nodes for connection to the motor to be controlled and connected to said switch control data lines; a stored-program-controlled processor means having an address output port connected to said memory address port for providing a page select address and having an address rate control port for providing an addressing rate select signal; a segment addressing means connected to said memory address port for sequentially addressing the segments of an addressed page at a selected addressing rate and connected to said address rate control port so as to provide a selected addressing rate in response to an addressing rate select signal provided from said processor means; and wherein said segment addressing means comprising a counter means connected to said memory address port, a programmable divider means connected to said counter means for providing a count input thereto and connected to said address rate control port for setting the divide ratio thereof in response to the address rate select signal, and pulse source means connected to said programmable divider means to provide a pulse input thereto.

Claim 6

A motor controlled for selectively controlling a poly-phase induction motor having at least two power phases by providing a controlled power waveform thereto of selected wave shape and frequency, said motor controller comprising: a waveform memory means divided into p addressable pages representing p available wave shapes with each page divided into s addressable segments, the segments of each page having binary switch control information stored therein, the pages and the segments of each page addressable through a memory address port to provide the so-addressed switch control information to switch control data lines; selectively gatable switch means connected between DC power source means to at least two output power nodes for connection to the motor to be controlled and connected to said switch control data lines; a stored-program-controlled processor means having an address output port connected to said memory address port for providing a page select address and having an address rate control port for providing an addressing rate select signal; a segment addressing means connected to said memory address port for sequentially addressing the segments of an addressed page at a selected addressing rate and connected to said address rate control port so as to provide a selected addressing rate in response to an addressing rate select signal provided from said processor means; and wherein said segment addressing means comprising a counter means connected to said memory address port, a programmable divider means connected to said counter means for providing a count input thereto and connected to said address rate control port for setting the divide ratio thereof in response to the address rate select signal, and pulse source means connected to said programmable divider means to provide a pulse input thereto.

Claim 7

The motor controller claimed in claims 1, 2, or 3 wherein said processor means further includes an input port means for receiving waveform determining information from an external device.

Claim 8

The motor controller claimed in claim 4, wherein said external device comprises a key pad.

Claim 9

The motor controller claimed in claim 4, wherein said external device comprises a trigger-switch.

Claim 10

The motor controller claimed in claim 4, wherein said external device includes at least one condition responsive transducer.

Claim 11

The motor controller claimed in claim 4, wherein said external device includes an increment/decrement switch.

Claim 12

The motor controller claimed in claims 1, 2, or 3 wherein each page of said memory contain binary switching information for synthesizing the first half of a waveform and means for complementing the binary switching information for synthesizing the second half of a waveform.

Claim 13

A waveform synthesizer for providing a waveform of selected frequency and wave shape for driving an AC waveform utilizing device, said waveform synthesizer comprising: a waveform memory means divided into p addressable pages representing p available wave shapes with each page divided into s addressable segments, the segments of each page having binary switch control information stored therein, the pages and the segments of each page addressable through a memory address port to provide the so-addressed switch control information to switch control data lines; selectively gatable switch means connected between a DC power source means to at least one output power node for connection to the motor to be controlled and connected to said switch control data lines; stored-program control means connected to said waveform memory for (a) addressing a selected one of the pages available in the waveform memory, and (b) sequentially addressing the segments of the addressed page at a selected sequential address rate to thereby cause the gatable switch means to switch DC power to the output node to synthesize a waveform of selected waveform and wave shape in accordance with the stored binary switch control information of the addressed page; said stored program control means including a stored-program-controlled processor means having an address output port connected to said memory address port for providing a page select address and having an address rate control port for providing an addressing rate select signal, and a segment addressing means connected to said memory address port for sequentially addressing the segments of an addressed page at a selected addressing rate and connected to said address rate control port so as to provide a selected addressing rate in response to an addressing rate select signal provided from said processor means; and wherein said segment addressing means comprising a presettable frequency divider connected to a source of input pulses with the frequency divide rate set by said processor through said segment address rate select port, said presettable frequency divider connected and providing frequency divided input pulses to a segment address counter connected to said memory address port.

Claim 14

A waveform synthesizer for providing a waveform of selected frequency and wave shape for driving an AC waveform utilizing device, said waveform synthesizer comprising: a waveform memory means divided into p addressable pages representing p available wave shapes with each page divided into s addressable segments, the segments of each page having binary switch control information stored therein, the pages and the segments of each page addressable through a memory address port to provide the so-addressed switch control information to switch control data lines; selectively gatable switch means connected between a DC power source means to at least one output power node for connection to the motor to be controlled and connected to said switch control data lines; stored-program control means connected to said waveform memory for (a) addressing a selected one of the pages available in the waveform memory, and (b) sequentially addressing the segments of the addressed page at a selected sequential address rate to thereby cause the gatable switch means to switch DC power to the output node to synthesize a waveform of selected waveform and wave shape in accordance with the stored binary switch control information of the addressed page; said stored program control means including a stored-program-controlled processor means having an address output port connected to said memory address port for providing a page select address and having an address rate control port for providing an addressing rate select signal, and a segment addressing means connected to said memory address port for sequentially addressing the segments of an addressed page at a selected addressing rate and connected to said address rate control port so as to provide a selected addressing rate in response to an addressing rate select signal provided from said processor means; and wherein said segment addressing means comprising a presettable frequency divider connected to a source of input pulses with the frequency divide rate set by said processor through said segment address rate select port, said presettable frequency divider connected and providing frequency divided input pulses to a segment address counter connected to said memory address port.

Claim 15

A waveform synthesizer for selectively controlling an AC machine by providing a controlled power waveform thereto of selected wave shape and frequency, said waveform synthesizer comprising: a waveform memory means divided into p addressable pages representing p available wave shapes with each page divided into s addressable segments, the segments of each page having binary switch control information stored therein, the pages and the segments of each page addressable through a memory address port to provide the so-addressed switch control information to switch control data lines; selectively gatable switch means connected between a DC power source means to at least two output power nodes for connection to the motor to be controlled and connected to said switch control data lines; stored-program control means connected to said waveform memory for (a) addressing a selected one of the pages available in the waveform memory, and (b) sequentially addressing the segments of the addressed page at a selected sequential address rate to thereby cause the gatable switches to switch DC power to the output node to synthesize a waveform of selected waveform and wave shape in accordance with the stored binary switch control information of the addressed page; said stored program control means including a stored-program-controlled processor means having an address output port connected to said memory address port for providing a page select address and having an address rate control port for providing an addressing rate select signal, and a segment addressing means connected to said memory address port for sequentially addressing the segments of an addressed page at a selected addressing rate and connected to said address rate control port so as to provide a selected addressing rate in response to an addressing rate select signal provided from said processor means; and wherein said segment addressing means comprising a presettable frequency divider connected to a source of input pulses with the frequency divide rate set by said processor through said segment address rate select port, said presettable frequency divider connected and providing frequency divided input pulses to a segment address counter connected to said memory address port.

Claim 16

A waveform synthesizer for selectively controlling an AC machine by providing a controlled power waveform thereto of selected wave shape and frequency, said waveform synthesizer comprising: a waveform memory means divided into p addressable pages representing p available wave shapes with each page divided into s addressable segments, the segments of each page having binary switch control information stored therein, the pages and the segments of each page addressable through a memory address port to provide the so-addressed switch control information to switch control data lines; selectively gatable switch means connected between a DC power source means to at least two output power nodes for connection to the motor to be controlled and connected to said switch control data lines; stored-program control means connected to said waveform memory for (a) addressing a selected one of the pages available in the waveform memory, and (b) sequentially addressing the segments of the addressed page at a selected sequential address rate to thereby cause the gatable switches to switch DC power to the output node to synthesize a waveform of selected waveform and wave shape in accordance with the stored binary switch control information of the addressed page; said stored program control means including a stored-program-controlled processor means having an address output port connected to said memory address port for providing a page select address and having an address rate control port for providing an addressing rate select signal, and a segment addressing means connected to said memory address port for sequentially addressing the segments of an addressed page at a selected addressing rate and connected to said address rate control port so as to provide a selected addressing rate in response to an addressing rate select signal provided from said processor means; and wherein said segment addressing means comprising a presettable frequency divider connected to a source of input pulses with the frequency divide rate set by said processor through said segment address rate select port, said presettable frequency divider connected and providing frequency divided input pulses to a segment address counter connected to said memory address port.

Claim 17

A waveform synthesizer for selectively controlling an AC machine having at least two power phases by providing a controlled power waveform thereto of selected wave shape and frequency, said waveform synthesizer comprising: a waveform memory means divided into p addressable pages representing p available wave shapes with each page divided into s addressable segments, the segments of each page having binary switch control information stored therein, the pages and the segments of each page addressable through a memory address port to provide the so-addressed switch control information to switch control data lines; selectively gatable switch means connected between DC power source means to at least two output power nodes for connection to the AC machine to be controlled and connected to said switch control data lines; a stored-program-controlled processor means having an address output port connected to said memory address port for providing a page select address and having an address rate control port for providing an addressing rate select signal; a segment addressing means connected to said memory address port for sequentially addressing the segments of an addressed page at a selected addressing rate and connected to said address rate control port so as to provide a selected addressing rate in response to an addressing rate select signal provided from said processor means; and wherein said segment addressing means comprising a counter means connected to said memory address port, a programmable divider means connected to said counter means for providing a count input thereto and connected to said address rate control port for setting the divide ratio thereof in response to the address rate select signal, and pulse source means connected to said programmable divider means to provide a pulse input thereto.

Claim 18

A waveform synthesizer for selectively controlling an AC machine having at least two power phases by providing a controlled power waveform thereto of selected wave shape and frequency, said waveform synthesizer comprising: a waveform memory means divided into p addressable pages representing p available wave shapes with each page divided into s addressable segments, the segments of each page having binary switch control information stored therein, the pages and the segments of each page addressable through a memory address port to provide the so-addressed switch control information to switch control data lines; selectively gatable switch means connected between DC power source means to at least two output power nodes for connection to the AC machine to be controlled and connected to said switch control data lines; a stored-program-controlled processor means having an address output port connected to said memory address port for providing a page select address and having an address rate control port for providing an addressing rate select signal; a segment addressing means connected to said memory address port for sequentially addressing the segments of an addressed page at a selected addressing rate and connected to said address rate control port so as to provide a selected addressing rate in response to an addressing rate select signal provided from said processor means; and wherein said segment addressing means comprising a counter means connected to said memory address port, a programmable divider means connected to said counter means for providing a count input thereto and connected to said address rate control port for setting the divide ratio thereof in response to the address rate select signal, and pulse source means connected to said programmable divider means to provide a pulse input thereto.

Claim 19

The waveform synthesizer claimed in claims 10, 11, or 12 wherein said processor means further includes an input port means for receiving waveform determining information from an external device.

Claim 20

The waveform synthesizer claimed in claims 10, 11, or 12 wherein each page of said memory contain binary switching information for synthesizing the first half of a waveform and means for complementing the binary switching information for synthesizing the second half of a waveform.