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US4668879A Expired / Lapsed US ⏱️ 0.0 years remaining

Dotted "or" function for current controlled gates

Assignee: International Business Machines Corp
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Filing: 1986-02-10
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Granted: 1987-05-26
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Expires: 2006-02-10
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Abstract

Abstract A "dotted or" logic circuit comprising Current Controlled Gate (CCG) circuits is described. In accordance with the present invention, Schottky diodes are cross-coupled between the dotted CCG circuits. Specifically, a Schottky diode is connected between the base of the base-to-collector diode of one CCG circuit to the emitter of the input transistors of another CCG circuit and vice versa.

Inventors

  • 👤 Allan H. Dansky
  • 👤 Martine M. F. Savalle
  • 👤 Helmut Schettler

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-07 20:42
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/013; H03K19/0136; H03K19/02; H03K19/08; H03K19/082; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; H03K3/2885

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 140 words
A dotted "or" logic circuit which comprises: at least a first and a second current-controlled gate (CCG) circuit, each comprising an input section which includes at least one bipolar input transistor, an output section for making a dotted "or" connection, and means for coupling the input section to the output section, the coupling means having a capacitance, and a first and a second discharging means, the first discharging means being connected at one end to the coupling means of the first CCG circuit and at the other end to the emitter of the at least one input transistor of the second CCG circuit, the second discharging means being connected at one end to coupling means of the second CCG circuit and at the other end to the emitter of the at least one input transistor of the first CCG circuit.
Claim 2
Dependent Claim 140 words
A dotted "or" logic circuit which comprises: at least a first and a second current-controlled gate (CCG) circuit, each comprising an input section which includes at least one bipolar input transistor, an output section for making a dotted "or" connection, and means for coupling the input section to the output section, the coupling means having a capacitance, and a first and a second discharging means, the first discharging means being connected at one end to the coupling means of the first CCG circuit and at the other end to the emitter of the at least one input transistor of the second CCG circuit, the second discharging means being connected at one end to coupling means of the second CCG circuit and at the other end to the emitter of the at least one input transistor of the first CCG circuit.
Claim 3
Dependent Claim 17 words
A dotted "or" logic circuit in accordance with claim 1 wherein the coupling means is a diode.
Claim 4
Dependent Claim 28 words
A dotted "or" logic circuit in accordance with claim 2 wherein the diode is the base-to-collector junction of a bipolar transistor which has its base and emitter short-circuited.
Claim 5
Dependent Claim 18 words
A dotted "or" logic circuit in accordance with claim 3 wherein the discharging means is a Schottky diode.
Claim 6
Dependent Claim 160 words
A latch circuit which comprises: at least one first current-controlled gate (CCG) circuit comprising an input section which includes at least two bipolar input transistors, and an output section coupled to said input section, a second CCG circuit comprising an input section which includes at least two inputs, an output section, and means for coupling the input section to the output section, the coupling means having a capacitance, the output sections of the first and second CCG circuits being dot "or"ed to provide a first output, the first output being input to an inverter to provide a second output, the second output being connected to one of the at least two inputs of the second CCG circuit, and a discharging means being connected at one end to the coupling means of the second CCG circuit and at the other end to the emitter of one of the at least two input transistors of the at least one first CCG circuit.
Claim 7
Dependent Claim 160 words
A latch circuit which comprises: at least one first current-controlled gate (CCG) circuit comprising an input section which includes at least two bipolar input transistors, and an output section coupled to said input section, a second CCG circuit comprising an input section which includes at least two inputs, an output section, and means for coupling the input section to the output section, the coupling means having a capacitance, the output sections of the first and second CCG circuits being dot "or"ed to provide a first output, the first output being input to an inverter to provide a second output, the second output being connected to one of the at least two inputs of the second CCG circuit, and a discharging means being connected at one end to the coupling means of the second CCG circuit and at the other end to the emitter of one of the at least two input transistors of the at least one first CCG circuit.
Claim 8
Dependent Claim 14 words
A latch in accordance with claim 5 wherein the coupling means is a diode.
Claim 9
Dependent Claim 25 words
A latch in accordance with claim 6 wherein the diode is the base-to-collector junction of a bipolar transistor which has its base and emitter short-circuited.
Claim 10
Dependent Claim 15 words
A latch in accordance with claim 7 wherein the discharging means is a Schottky diode.
Claim 11
Dependent Claim 14 words
A latch in accordance with claim 8 wherein the inverter is a CCG circuit.

References Cited (Backward Citations)

US3450896A Cited
US3505535A Cited
US3614467A Cited
US3814953A Cited
US4215418A Cited
US4251737A Cited
US4319148A Cited
US4376900A Cited
US4529896A Cited
US4424455A Cited
US4605870A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1990-05-25 1990-11-24 1991-05-26 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1994-05-25 1994-11-24 1995-05-26 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1998-05-25 1998-11-24 1999-05-26 $7700.00 Window Closed / Lapsed

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