Method of interconnecting wiring planes

Claim 1

For microelectronics apparatus, a method of fabricating customized connections between wiring planes, each plane having multiple conductors, the method comprising: forming a first wiring plane having multiple conductors; forming an insulating layer that overlies and electrically insulates the first wiring plane; forming a second wiring plane that overlies the insulating layer by forming multiple conductors that are selectively electrically connected to the first wiring plane, selected conductors of each wiring plane being electrically connected to selected conductors of the other wiring plane; and modifying said connections by electrically disconnecting selected ones of the electrical connections between the first and second wiring planes to customize the electrical connections.

Claim 12

A method of fabricating customized interconnections in an integrated circuit package or integrated circuit chip between wiring planes superposed on a substrate, each plane having multiple conductors, the method comprising forming a first wiring plane upon the substrate by forming a plurality of generally parallel electrically conductive strips; forming an insulating layer that overlies and electrically insulates the first wiring plane; forming openings in said insulating layer at selected locations to expose selected portions of the underlying first wiring plane to accommodate electrical connections therewith; forming a second wiring plane that overlies the insulating layer and makes electrical connection with the underlying first wiring plane by forming a plurality of generally parallel electrically conductive strips, each conductor of each wiring plane being electrically connected to each conductor of the other wiring plane; and modifying said connections by electrically disconnecting selected ones of the electrical connections between the first and second wiring planes to customize the electrical interconnections.

Claim 13

A method of fabricating customized interconnections in an integrated circuit package or integrated circuit chip between wiring planes superposed on a substrate, each plane having multiple conductors, the method comprising forming a first wiring plane upon the substrate by forming a plurality of generally parallel electrically conductive strips; forming an insulating layer that overlies and electrically insulates the first wiring plane; forming openings in said insulating layer at selected locations to expose selected portions of the underlying first wiring plane to accommodate electrical connections therewith; forming a second wiring plane that overlies the insulating layer and makes electrical connection with the underlying first wiring plane by forming a plurality of generally parallel electrically conductive strips, each conductor of each wiring plane being electrically connected to each conductor of the other wiring plane; and modifying said connections by electrically disconnecting selected ones of the electrical connections between the first and second wiring planes to customize the electrical interconnections.