Semiconductor memory device

Claim 1

A semiconductor memory device comprising: a semiconductor memory array having a plurality of memory cells arranged in a matrix for storing data in response to an external write enable signal; a data line coupled with said memory array through switching means which transfers data on said data line to and from said memory array; a data input circuit coupled with said data line for writing information in a selected memory cell in said memory array; a data output circuit coupled with said data line for coupling information read out of a selected memory cell to an output; such that said data line is utilized for both writing information into said array during a memory write cycle, and reading information from said array during a memory read cycle; wherein the improvement comprises; a self-diagnosis means also coupled with said data line and having a storage means for storing during an early portion of said write cycle the data on said data line which is also stored in a selected memory cell of said memory array; and a comparison means for comparing, after the data is no longer applied to said memory cell and during a later portion of said write cycle, data out of said selected memory cell with the data that was stored in said storage means during said early portion of said write cycle; whereby when said data for the selected memory cell does not coincide with the data stored in said storage means, said self-diagnosis means provides an error signal.