Error corrector for a linear feedback shift register sequence

Claim 2

A circuit for correcting errors in a rate-one orthogonal convolutional code which further operates as a synchronization signal, comprising: open loop linear feedback shift register means having an input port for receiving a synchronization signal and a plurality of output ports arranged and combined to form a feedback signal; first combining means for combining said synchronization signal and said feedback signal to form an intermediate signal, which combined with a syndrome correction signal forms an error estimation signal; syndrome register means having a first input port for receiving said error estimation signal and a plurality of additional input ports for receiving said syndrome correction signal, said syndrome register means providing a plurality of output syndrome signals; majority decoder means for selectively receiving said intermediate signal and said output syndrome signals to provide said syndrome correction signal when a predetermined threshold is exceeded; and second combining means for combining said syndrome correction signal and a further output signal from said open loop linear feedback shift register means to yield a corrected synchronization signal.

Claim 3

The circuit of claim 1 wherein said first combining means further comprises: first binary summing means for receiving said synchronization signal and said feedback signal to provide said intermediate signal; second binary summing means for receiving said intermediate signal and said correction signal to yield said syndrome signal.

Claim 4

The combining means of claim 2, wherein said first and second binary summing means further comprises exclusive "OR" logic gates.

Claim 5

The circuit of claim 1, wherein said second combining means further comprises a binary summing means.

Claim 6

The combining means of claim 4 wherein said binary summer comprises an exclusive "OR" logic gate.

Claim 7

The circuit of claim 1, wherein the length of said open loop linear feedback shift register means and said syndrome register means are identical.

Claim 8

The circuit of claim 1, wherein said threshold of said majority decoder means is equal to M/2+1, where M equals the number of inputs ports of said majority decoder means.

Claim 9

In a synchronous data communication system having at least one transmitter, which interleaves a synchronization signal with an information signal, and at least one receiver, the improvement comprising: at the transmitter: closed loop linear feedback shift register means having a plurality of outputs arranged and combined to form a feedback signal, and an input port for receiving said feedback signal, for providing a rate-one orthogonal convolutional code which represents the synchronization signal; and at the receiver: open loop linear feedback shift register means having an input port for receiving a synchronization signal and a plurality of output ports arranged and combined to form a feedback signal; first combining means for combining said synchronization signal and said feedback signal to form an intermediate signal, which combined with a syndrome correction signal forms and error estimation signal; syndrome register means having a first input port for receiving said error estimation signal and a plurality of additional input ports for receiving a correction signal, said syndrome register means providing a plurality of output syndrome signals; majority decoder means for selectively receiving said intermediate signal and said output syndrome signals to provide said syndrome correction signal when a predetermined threshold is exceeded; and second combining means for combining said syndrome correction signal and a further output signal from said open loop linear feedback shift register means to yield a corrected synchronization signal.

Claim 10

In a synchronous data communication system having at least one transmitter, which interleaves a synchronization signal with an information signal, and at least one receiver, the improvement comprising: at the transmitter: closed loop linear feedback shift register means having a plurality of outputs arranged and combined to form a feedback signal, and an input port for receiving said feedback signal, for providing a rate-one orthogonal convolutional code which represents the synchronization signal; and at the receiver: open loop linear feedback shift register means having an input port for receiving a synchronization signal and a plurality of output ports arranged and combined to form a feedback signal; first combining means for combining said synchronization signal and said feedback signal to form an intermediate signal, which combined with a syndrome correction signal forms and error estimation signal; syndrome register means having a first input port for receiving said error estimation signal and a plurality of additional input ports for receiving a correction signal, said syndrome register means providing a plurality of output syndrome signals; majority decoder means for selectively receiving said intermediate signal and said output syndrome signals to provide said syndrome correction signal when a predetermined threshold is exceeded; and second combining means for combining said syndrome correction signal and a further output signal from said open loop linear feedback shift register means to yield a corrected synchronization signal.

Claim 11

In a synchronous data communication system having at least one transmitter, which provides a synchronization signal on an independent synchronization channel, and at least one receiver, the improvement comprising: at the transmitter: closed loop linear feedback shift register means having a plurality of outputs arranged and combined to form a feedback signal, and an input port for receiving said feedback signal, for providing a orthogonal convolutional code which represents the synchronization signal; and at the receiver: open loop linear feedback shift register means having an input port for receiving a synchronization signal and a plurality of output ports arranged and combined to form a feedback signal; first combining means for combining said synchronization signal and, said feedback signal to form an intermediate signal, which combined with a syndrome correction signal forms an error estimation signal; syndrome register means having a first input port for receiving said error estimation signal and a plurality of additional input ports for receiving said syndrome correction signal, said syndrome register means providing a plurality of output syndrome signals; majority decoder means for selectively receiving said intermediate signal and said output syndrome signals to provide said syndrome correction signal when a predetermined threshold is exceeded; and second combining means for combining said syndrome correction signal and a further output signal from said open loop linear feedback shift register means to yield a corrected synchronization signal.

Claim 12

In a synchronous data communication system having at least one transmitter, which provides a synchronization signal on an independent synchronization channel, and at least one receiver, the improvement comprising: at the transmitter: closed loop linear feedback shift register means having a plurality of outputs arranged and combined to form a feedback signal, and an input port for receiving said feedback signal, for providing a orthogonal convolutional code which represents the synchronization signal; and at the receiver: open loop linear feedback shift register means having an input port for receiving a synchronization signal and a plurality of output ports arranged and combined to form a feedback signal; first combining means for combining said synchronization signal and, said feedback signal to form an intermediate signal, which combined with a syndrome correction signal forms an error estimation signal; syndrome register means having a first input port for receiving said error estimation signal and a plurality of additional input ports for receiving said syndrome correction signal, said syndrome register means providing a plurality of output syndrome signals; majority decoder means for selectively receiving said intermediate signal and said output syndrome signals to provide said syndrome correction signal when a predetermined threshold is exceeded; and second combining means for combining said syndrome correction signal and a further output signal from said open loop linear feedback shift register means to yield a corrected synchronization signal.