Abstract An input data signal, in which n data words W 1 to W n and two check words P and Q are treated as one data block, is processed by P and Q decoding circuits. The decoded data S 1 and T i- (n+1) S 2 from the decoding circuits are added to each other in an adder to generate S 1 +T i (n+1) S 2 which is in turn selected by a gate circuit in accordance with a selection signal. The selection signal is supplied from an M matrix generator (MG) embodied as a linear feedback shift register for H(x)=X m +X g +1. The initial value of the linear feedback shift register is set in accordance with the error word data derived from an error word control circuit and the order of the data to be decoded. The decoded data sequentially selected from the gate circuit are added by an adder to be the data W je to be decoded, while at the same time those are added to the S 1 by an adder to be the data W ie to be decoded. The data W je and W ie is added to the corresponding data words W i and W j of the input data signal having passed through a one-block delay circuit by an adder, whereby the error data are corrected.
An error data correcting system in which a group of n data words (W 1 ) through (W n ) each including m bits has associated therewith a P check code ##EQU33## and a Q check code ##EQU34## the system being capable of correcting erroneous data words W ie and W je , the system comprising: first means for decoding said P check code to generate a first syndrome data word S 1 ; second means for decoding said Q check code to generate a second syndrome data word S 2 ; first means for summing corresponding bits in said syndrome data words S 1 and S 2 to produce a syndrome sum data word; M matrix generator means for generating an M matrix corresponding to M(x)=X m +X g +1; means for controlling said M matrix generator means to produce M matrix selector signals; second means for summing said syndrome sum data word and said M matrix selector signal to generate a first intermediate data word W jc ; third means for summing W je and S 1 to generate a second intermediate data word, W ic ; and means for combining (1) the data words W je and W jc to produce corrected data word W j , and (2) the data words W ie and W ic to produce the corrected data word W i .
Claim 2
Dependent Claim
229 words
An error data correcting system in which a group of n data words (W 1 ) through (W n ) each including m bits has associated therewith a P check code ##EQU33## and a Q check code ##EQU34## the system being capable of correcting erroneous data words W ie and W je , the system comprising: first means for decoding said P check code to generate a first syndrome data word S 1 ; second means for decoding said Q check code to generate a second syndrome data word S 2 ; first means for summing corresponding bits in said syndrome data words S 1 and S 2 to produce a syndrome sum data word; M matrix generator means for generating an M matrix corresponding to M(x)=X m +X g +1; means for controlling said M matrix generator means to produce M matrix selector signals; second means for summing said syndrome sum data word and said M matrix selector signal to generate a first intermediate data word W jc ; third means for summing W je and S 1 to generate a second intermediate data word, W ic ; and means for combining (1) the data words W je and W jc to produce corrected data word W j , and (2) the data words W ie and W ic to produce the corrected data word W i .
Claim 3
Dependent Claim
20 words
A data correcting system according to claim 1 wherein said M matrix generator means comprises a linear feedback shift register.
Claim 4
Dependent Claim
51 words
A data correcting system according to claim 2 wherein said controlling means includes means for setting said linear feedback shift register to a value corresponding to the difference in relative positions i, j of said erroneous data words W ie and W je respectively, in said group of n data words.
Claim 5
Dependent Claim
53 words
A data correcting system according to claim 2 wherein said linear feedback shift register has a forward shift direction and a reverse shift direction and wherein said controlling means includes means for establishing an initial value in said linear feedback shift register by shifting the contents thereof one position in said reverse direction.