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US4667215A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Meidensha Corp
•
Filing: 1985-05-17
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Granted: 1987-05-19
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Expires: 2005-05-17
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Abstract

Abstract In manufacturing a GTO, a silicon wafer is cut away along one of the crystal planes indicated by {100} in Miller indices, and the burried gate or the current channels are so arranged on the crystal plane that at least one longitudinal direction thereof is substantially in parallel with at least one of axes indicated by <100> on condition that the inner product of the plane vector and the axis vector is zero. In the GTO thus manufactured, it is possible to minimize the crystal defect density on the crystal plane and thus to realize the GTOs having uniform turned-on voltage, in particular, while increasing the controllable current markedly. P

Inventors

  • 👤 Takayasu Kawamura
  • 👤 Yasuhide Hayashi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 09:32
CPC Classifications
H; H10; H10D; H10D18/00; H10D18/60; H10D62/00; H10D62/10; H10D62/17; H10D62/192; H10D62/206; H10D62/213; H10D62/221; H10D62/328; H10D62/343; H10D62/40; H10D62/405

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 203 words
In a semiconductor switching device having at least three alternate semiconductor layers formed substantially in parallel with a crystal plane indicated by {100 } in Miller indices; a high impurity atom concentration control layer P 2 ++ buried in one of said at least three alternate semiconductor layers; and a plurality of long and narrow current channels CH formed in said high impurity atom concentration control layer P 2 ++ , an anode A and a cathode k being formed on either outer side of said at least three alternate semiconductor layers, an anode current flowing from said anode A to said cathode k through said current channels CH perpendicularly to the crystal plane indicated by {100 } being controlled by a control current flowing through said high impurity atom concentration control layer P 2 ++ in a direction substantially parallel to the crystal plane indicated by {100 }, the improvement wherein plural longitudinal directions of said current channels CH formed in said high impurity atom concentration control layer P 2 ++ are substantially in parallel with at least one of crystal axes indicated by <100> on condition that inner product of a crystal axis vector and a crystal plane vector is zero.
Claim 2
Dependent Claim 203 words
In a semiconductor switching device having at least three alternate semiconductor layers formed substantially in parallel with a crystal plane indicated by {100 } in Miller indices; a high impurity atom concentration control layer P 2 ++ buried in one of said at least three alternate semiconductor layers; and a plurality of long and narrow current channels CH formed in said high impurity atom concentration control layer P 2 ++ , an anode A and a cathode k being formed on either outer side of said at least three alternate semiconductor layers, an anode current flowing from said anode A to said cathode k through said current channels CH perpendicularly to the crystal plane indicated by {100 } being controlled by a control current flowing through said high impurity atom concentration control layer P 2 ++ in a direction substantially parallel to the crystal plane indicated by {100 }, the improvement wherein plural longitudinal directions of said current channels CH formed in said high impurity atom concentration control layer P 2 ++ are substantially in parallel with at least one of crystal axes indicated by <100> on condition that inner product of a crystal axis vector and a crystal plane vector is zero.
Claim 3
Dependent Claim 19 words
The semiconductor switching device as set forth in claim 1, wherein said switching device is a gate turn-off thyristor.
Claim 4
Dependent Claim 17 words
The semiconductor switching device as set forth in claim 1, wherein said switching device is a thyristor.
Claim 5
Dependent Claim 19 words
The semiconductor switching device as set forth in claim 1, wherein said switching device is a static induction transistor.
Claim 6
Dependent Claim 19 words
The semiconductor switching device as set forth in claim 1, wherein said switching device is an field effect transistor.
Claim 7
Dependent Claim 268 words
In a gate turn-off thyristor having four alternately-different PNPN semiconductor layers of: (a) a first P-type layer P 1 having an anode; (b) a first N-type layer N 1 adjoining to the first P-type layer P 1 ; and (c) a second P-type layer including: a first impurity atom concentration layer P 2 adjoining to the first N-type layer N 1 ; a second impurity atom concentration layer P 2 - adjoining to the first impurity atom concentration layer P 2 , a second concentration in the second impurity atom concentration layer P 2 - being lower than a first concentration in the first impurity atom concentration layer P 2 ; and a third low-resistance impurity atom concentration layer P 2 ++ buried in the first impurity atom concentration layer P 2 and between the first and second layers P 2 and P 2 - , current channels CH being formed between the third low resistance layers P 2 ++ ; and (d) a second N-type layer N 2 formed in the second impurity atom concentration layer P 2- and having a cathode, the improvement wherein said third low-resistance impurity atom concentration layer P 2 ++ is formed on a crystal plane indicated by {100 } in Miller indices and at least one longitudinal direction of the current channels CH formed between the third low resistance layers P 2 ++ is arranged substantially in parallel with at least one of crystal axes indicated by <100> on the crystal plane {100 } on condition that inner product of the crystal axis vector and the crystal plane vector is zero.
Claim 8
Dependent Claim 268 words
In a gate turn-off thyristor having four alternately-different PNPN semiconductor layers of: (a) a first P-type layer P 1 having an anode; (b) a first N-type layer N 1 adjoining to the first P-type layer P 1 ; and (c) a second P-type layer including: a first impurity atom concentration layer P 2 adjoining to the first N-type layer N 1 ; a second impurity atom concentration layer P 2 - adjoining to the first impurity atom concentration layer P 2 , a second concentration in the second impurity atom concentration layer P 2 - being lower than a first concentration in the first impurity atom concentration layer P 2 ; and a third low-resistance impurity atom concentration layer P 2 ++ buried in the first impurity atom concentration layer P 2 and between the first and second layers P 2 and P 2 - , current channels CH being formed between the third low resistance layers P 2 ++ ; and (d) a second N-type layer N 2 formed in the second impurity atom concentration layer P 2- and having a cathode, the improvement wherein said third low-resistance impurity atom concentration layer P 2 ++ is formed on a crystal plane indicated by {100 } in Miller indices and at least one longitudinal direction of the current channels CH formed between the third low resistance layers P 2 ++ is arranged substantially in parallel with at least one of crystal axes indicated by <100> on the crystal plane {100 } on condition that inner product of the crystal axis vector and the crystal plane vector is zero.
Claim 9
Dependent Claim 62 words
The gate turn-off thyristor as set forth in claim 6, wherein said third low-resistance impurity atom concentration layer P 2 ++ is formed on a specific silicon crystal plane indicated by (100) and the longitudinal direction of the current channels CH is arranged substantially in parallel with a specific silicon crystal axis indicated by [010] on the specific silicon crystal plane (100).
Claim 10
Dependent Claim 61 words
The gate turn-off thyristor as set forth in claim 6, wherein said third low resistance impurity atom concentration layer P 2 ++ is formed on a specific silicon crystal plane (100) and the longitudinal direction of the current channels CH is arranged substantially in parallel with a specific silicon crystal axis indicated by [001] on the specific silicon crystal plane (100).
Claim 11
Dependent Claim 67 words
The gate turn-off thyristor as set forth in claim 6, wherein said third low resistance impurity atom concentration layer P 2 ++ is divided into four portions in a specific silicon crystal plane (100) and the longitudinal directions of biaxial current channels CH are arranged substantially in parallel with two specific silicon crystal axes indicated by [010], and [001] on the specific silicon crystal plane (100), respectively.
Claim 12
Dependent Claim 26 words
In the semiconductor switching device as set forth in claim 1, wherein a crystal for forming said at least three alternate semiconductor layers is crystallographically isotropic.

References Cited (Backward Citations)

DD74592A Cited
US3798513A Cited
US3821783A Cited
US3999211A Cited
US4171995A Cited
US3998674A Cited
GB2000640A Cited
EP0008535A2 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1990-05-18 1990-11-17 1991-05-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1994-05-18 1994-11-17 1995-05-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1998-05-18 1998-11-17 1999-05-19 $7700.00 Window Closed / Lapsed

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