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US4667184A
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Apparatus for counting enumeration input pulses
Assignee: Nippon Signal Co Ltd
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Filing: 1985-03-18
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Granted: 1987-05-19
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Expires: 2005-03-18
Abstract
Abstract In an apparatus for counting enumeration input pulses according to the present invention, an enumeration input pulse is put in parallel in a plurality of stages of logical product computing oscillator means, and counting in the logical product computing oscillator means of the subsequent stage is advanced on condition that an output of termination of counting is put out from the logical product computing oscillator means of the precedent stage. For this purpose, delay means is arranged after the logical product computing oscillator means to set the time from the point of output of the logical product computing oscillator means of the precedent stage to the point of termination of a predetermined delay time so that this time is longer than the width of the enumeration input pulse and shorter than the frequency thereof. Furthermore, the logical product computing oscillator means makes an error at a time of a circuit failure in such a manner that no output is generated, and the delay time and enumeration input pulse make an error at a time of a circuit failure in such a way that a fail-safe effect is attained. Accordingly, enumeration input pulses can be counted with a fail-safe effect.
Inventors
- 👤 Koichi Futsuhara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 18:39
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/40; H03K23/50
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
453 words
An apparatus for counting enumeration input pulses, which comprises counting instruction generation means and a sequence of a plurality of stages of unit counting means, each unit counting means including; enumeration input pulse generating means for generating an enumeration input pulse having a predetermined pulse width, logical product computing oscillator means receiving an enumeration input pulse and arranged for making an error in such a way that an output is generated when a fault occurs in a circuit, rectifying means for rectifying an output of said logical product computing oscillator means, first delay means arranged subsequently to sid rectifying means, said first delay means arranged for making an error at a time of a fault in such a way that a delay time T1 thereof is not shortened, self-retention means for feeding back an output of said first delay means as an input to the logical product computing oscillator means to effect self-retention of oscillation in said logical product computing oscillator means, and second delay means for putting out the output of said first delay means with a delay time T2, the time from the output of said rectifying means to the point of termination of said delay time T2 being longer than a width T3 of the enumeration input pulse but shorter than a period T4 of the enumeration input pulse, means to determine the delay time T2 and the width of the enumeration input pulse so that an asymmetrical error is generated in such a way that the delay time and pulse width are prolonged or shortened to attain a fail-safe effect, means for inputting a counting instruction from said counting instruction generating means to said logical product computing oscillator means of the unit counting means of said first stage and for inputting the ouput of said second delay means of said unit counting means of a preceding stage to said logical product computing oscillator means of said unit counting means of a subsequent stage, and means for reversing the output of said logical product computing oscillator means of said unit counting means of the first stage to the same logic (oscillation or stopping of oscillation) as that of the first enumeration input pulse and for outputting with the counting instruction as the condition and on condition that the input pulse and the output signal of said second delay means of said unit counting means of the preceding stage are input with the same logical value, the output of said logical product computing oscillator means of said unit counting means of the subsequent stage is reversed to the same logic as the input signal and is put out, and said output of the rectifying means is used as an enumeration value.
Claim 2
Independent Claim
453 words
An apparatus for counting enumeration input pulses, which comprises counting instruction generation means and a sequence of a plurality of stages of unit counting means, each unit counting means including; enumeration input pulse generating means for generating an enumeration input pulse having a predetermined pulse width, logical product computing oscillator means receiving an enumeration input pulse and arranged for making an error in such a way that an output is generated when a fault occurs in a circuit, rectifying means for rectifying an output of said logical product computing oscillator means, first delay means arranged subsequently to sid rectifying means, said first delay means arranged for making an error at a time of a fault in such a way that a delay time T1 thereof is not shortened, self-retention means for feeding back an output of said first delay means as an input to the logical product computing oscillator means to effect self-retention of oscillation in said logical product computing oscillator means, and second delay means for putting out the output of said first delay means with a delay time T2, the time from the output of said rectifying means to the point of termination of said delay time T2 being longer than a width T3 of the enumeration input pulse but shorter than a period T4 of the enumeration input pulse, means to determine the delay time T2 and the width of the enumeration input pulse so that an asymmetrical error is generated in such a way that the delay time and pulse width are prolonged or shortened to attain a fail-safe effect, means for inputting a counting instruction from said counting instruction generating means to said logical product computing oscillator means of the unit counting means of said first stage and for inputting the ouput of said second delay means of said unit counting means of a preceding stage to said logical product computing oscillator means of said unit counting means of a subsequent stage, and means for reversing the output of said logical product computing oscillator means of said unit counting means of the first stage to the same logic (oscillation or stopping of oscillation) as that of the first enumeration input pulse and for outputting with the counting instruction as the condition and on condition that the input pulse and the output signal of said second delay means of said unit counting means of the preceding stage are input with the same logical value, the output of said logical product computing oscillator means of said unit counting means of the subsequent stage is reversed to the same logic as the input signal and is put out, and said output of the rectifying means is used as an enumeration value.
Claim 3
Dependent Claim
161 words
An apparatus for counting enumeration input pulses according to claim 1, wherein said logical product computing oscillator means have two input terminals A and B and one output terminal C, an enumeration input pulse signal having a pulse of a logical value of "1" as an object to be counted and a feedback signal of said self-retention means are put in said input terminal A, a counting instruction signal of a logical value of "1" is put in the input terminal of said logical product computing oscillator means of the first stage from said counting instruction generating means, output signals of said second delay means of the precedent stages are put in said input terminal B of said logical product computing oscillator means of the subsequent stage, and an oscillation output is put out in said output terminal C under an "and" condition where binary values of a logical value of "1" are put in said input terminals A and B.
Claim 4
Dependent Claim
73 words
An apparatus for counting enumeration input pulses according to claim 2, wherein said second delay means makes an error at a time of a fault of any component thereof in such a way that the delay time T2 is not shortened and the enumeration input pulse signal makes an error at a time of a fault in such a way that the pulse width of a logical value of "1" is not prolonged.
Claim 5
Dependent Claim
87 words
An apparatus for counting enumeration input pulses according to claim 2, wherein said enumeration input pulse generating means has a double base diode connected between the input terminal and the ground through base resistors, an emitter of said double base diode is connected between a said resistor and a said capacitor of a series circuit having said resistor and said capacitor, which is connected between the input terminal and the ground, and a base voltage of said double base diode on the ground side is put out.
Claim 6
Dependent Claim
43 words
An apparatus for counting enumeration input pulses according to claim 2, wherein said first and second delay means are constructed so that the input signal is put in a 4terminal capacitor through a resistor and the output is take out from the capacitor.
Claim 7
Independent Claim
56 words
An apparatus for counting enumeration input pulses according to any of claims 2 through 5, further comprising a buzzer activated in response to a counting instruction and wherein the apparatus for counting is comprised in a timer means for stopping buzzer sounding after a predetermined time from a counting instruction generated in crossing alarm signal apparatus.
Claim 8
Dependent Claim
56 words
An apparatus for counting enumeration input pulses according to claim 1, wherein said counting instruction generating means puts out a set signal of said logical product computing oscillator means based on a signal rising from a logical value of "0" and uses a signal rising from a logical value of "1" as a counting instruction signal.
Claim 9
Dependent Claim
203 words
An apparatus for counting enumeration input pulses according to claim 1, wherein said logical product computing oscillator means has two input terminals A and B and one output terminal, a set signal of said counting instruction generating means and a feedback signal of said self-retention means are put in said input terminal A, an enumeration input pulse signal having a pulse of a logical value of "0" as an object to be counted and a counting instruction signal from said counting instruction generating means are put in said input terminal B of said logical product computing oscillator means of the first stage, oscillation from said output terminal C is stopped under such a condition that each of the counting instruction signals and enumeration input pulse signals becomes a logical value of "0", the enumeration input pulse signal and output signals of said second delay means of the precedent stage are put in the input terminals of said logical product computing oscillator means of the subsequent stages, and an oscillation output is stopped under such a condition that each of the enumeration input pulse signal and the output signal of said second delay means of the precedent stage becomes a logical value of "0".
Claim 10
Dependent Claim
41 words
An apparatus for counting enumeration input pulses according to claim 8, wherein said first delay means has an on-delay structure and the pulse width T5 of the set signal is longer than the delay time T1 of said first delay means.
Claim 11
Dependent Claim
52 words
An apparatus for counting enumeration input pulses according to claim 9, wherein said second delay means has an off-delay structure and the delay time T2 of said second delay means is longer than the width T3 of the enumeration input pulse and shorter than the period T4 of the enumeration input pulse.
Claim 12
Dependent Claim
69 words
An apparatus for counting enumeration input pulses according to claim 8, wherein said second delay means makes an error at the time of a fault in such a way that the delay time T2 is not prolonged, and the enumeration input pulse signal makes an error at the time of a fault in such a way that the pulse width of a logical value of "0" is not shortened.
Claim 13
Dependent Claim
130 words
An apparatus for counting enumeration input pulses according to claim 8, wherein said enumeration pulse generating means has a PUT connected between the input terminal and the ground through a diode and first and second resistors, the portion between said diode and said first resistor is connected to the ground through a first capacitor, the portion between said first and second resistor is connected to the ground through a second capacitor, the gate terminal of said PUT is connected to the dividing point for dividing the power source voltage by third and fourth resistors arranged in series between the power source voltage input terminal and the ground, said division point is used as an output terminal, and said input terminal is connected to said gate terminal through a differential circuit.
Claim 14
Dependent Claim
42 words
An apparatus for counting enumeration input pulses according to claim 8, wherein said first delay means has such a structure that the input signal is put in a 4-terminal capacitor through a resistance and an output is taken out from said capacitor.
Claim 15
Dependent Claim
49 words
An apparatus for counting enumeration input pulses according to claim 8, wherein said second delay means has such a structure that a resistor is interposed between the input terminal and output terminal and a capacitor is connected between the ground and the portion between said resistor and output terminal.
Claim 16
Independent Claim
52 words
An apparatus for counting enumeration input pulses according to any of claims 8 through 14, further comprising a buzzer and wherein the apparatus for counting is comprised in a timer means for starting sounding of said buzzer a predetermined time after occurrence of a predetermined event in a crossing alarm signal apparatus.
Claim 17
Dependent Claim
64 words
An apparatus for counting enumeration input pulses according to claim 2 or 8, wherein said logical product computing oscillator means has such a structure that a standard power source voltage is applied to said input terminal B and when a voltage exceeding the standard power source voltage is applied to said input terminal A, an oscillation output is generated from said output terminal C.
Claim 18
Dependent Claim
161 words
An apparatus for counting enumeration input pulses according to claim 2 or 8, wherein said logical product computing oscillator means comprises a first transistor connected between said input terminals A and B through a collector-resistor, a second transistor connected between said input terminals A and B through a collector-resistor, the collector voltage of said first transistor being put in the base of said second transistor, and a third transistor connected between said input terminal A and the power source earth through a collector-resistor and a second zener diode, the collector voltage of said second transistor being put in a base of said third transistor through a first zener diode, and the logical product computing oscillator means has such a structure that the voltage division value by the collectorresistor and said second zener diode is put in the base of said first transistor and said output terminal C is connected between said second zener diode and the collector of said third transistor.
Claim 19
Dependent Claim
176 words
In a counting apparatus for counting a number of pulses to generate output signals indicative of occurrence of a predetermined number of pulses, including oscillating means for oscillating at predetermined frequencies to generate pulses to be counted thereby to determine a time period for generating said output signals, the improvement comprising: a plurality of oscillators arranged in a sequence, feedback means for providing to respective first inputs of said oscillators a form of respective outputs of said oscillators rectified by rectifying means and delayed by first delay periods generated by first delay means, feedforward means for providing to respective second inputs of successive oscillators in said sequence a form of outputs of respective preceding oscillators rectified by said rectifying means and delayed by second delay periods generated by second delay means, and fail-safe means for assuring that the time period for generating said output signals is varied in only one direction upon failure of any of a plurality of circuit components of said oscillators, said rectifying means, said first delay means and said second delay means.
Claim 20
Dependent Claim
176 words
In a counting apparatus for counting a number of pulses to generate output signals indicative of occurrence of a predetermined number of pulses, including oscillating means for oscillating at predetermined frequencies to generate pulses to be counted thereby to determine a time period for generating said output signals, the improvement comprising: a plurality of oscillators arranged in a sequence, feedback means for providing to respective first inputs of said oscillators a form of respective outputs of said oscillators rectified by rectifying means and delayed by first delay periods generated by first delay means, feedforward means for providing to respective second inputs of successive oscillators in said sequence a form of outputs of respective preceding oscillators rectified by said rectifying means and delayed by second delay periods generated by second delay means, and fail-safe means for assuring that the time period for generating said output signals is varied in only one direction upon failure of any of a plurality of circuit components of said oscillators, said rectifying means, said first delay means and said second delay means.
Claim 21
Dependent Claim
110 words
An improved counting apparatus as recited in claim 18 further comprising alarm generating means for generating an alarm in response to said output signals, wherein said failsafe means comprises an arrangement of said circuit components of said oscillators, said rectifying means, and said first and second delay means for assuring that said alarm generating means will generate said alarm beginning at a time no later than a predetermined time from occurrence of a count triggering event and for assuring that upon failure of any of said circuit components any change resulting in said beginning time moves said beginning time closer to the time of occurrence of said count triggering event.
Claim 22
Dependent Claim
102 words
An improved counting apparatus as recited in claim 18 further comprising alarm generating means for generating an alarm in response to said output signals, wherein said failsafe means comprises an arrangement of said circuit components of said oscillators, said rectifying means, and said first and second delay means for assuring that said alarm generating means will generate said alarm for a time duration no shorter than a predetermined duration and for assuring that upon failure of any of said circuit components any change resulting in said time duration of the generated alarm causes an extension of the time duration of said alarm.
Claim 23
Dependent Claim
43 words
An improved counting apparatus as recited in claim 18 wherein said fail-safe means comprises an arrangement of said oscillators in said counting apparatus for assuring an output voltage of said oscillators at a predetermined level in response to failure of any component thereof.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-05-18 | 1990-11-17 | 1991-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-05-18 | 1994-11-17 | 1995-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-05-18 | 1998-11-17 | 1999-05-19 | $7700.00 | Window Closed / Lapsed |